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Merge pull request #31 from Links2004/esp8266
HardwareSerial rewrite for UART0 and UART1 support
This commit is contained in:
Ivan Grokhotkov
commit
52183b7df6
@ -17,8 +17,10 @@
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You should have received a copy of the GNU Lesser General Public
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License along with this library; if not, write to the Free Software
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Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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Modified 31 March 2015 by Markus Sattler (rewrite the code for UART0 + UART1 support in ESP8266)
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*/
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#include <stdlib.h>
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#include <stdio.h>
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@ -37,219 +39,428 @@ extern "C" {
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#include "HardwareSerial.h"
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HardwareSerial Serial;
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uart_t* uart0_init(int baud_rate);
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void uart0_set_baudrate(uart_t* uart, int baud_rate);
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int uart0_get_baudrate(uart_t* uart);
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void uart0_uninit(uart_t* uart);
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void uart0_transmit(uart_t* uart, const char* buf, size_t size); // may block on TX fifo
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void uart0_wait_for_transmit(uart_t* uart);
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void uart0_transmit_char(uart_t* uart, char c); // does not block, but character will be lost if FIFO is full
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void uart_set_debug(bool enabled);
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bool uart_get_debug();
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struct uart_
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{
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int baud_rate;
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};
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#define UART_TX_FIFO_SIZE 0x80
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void ICACHE_FLASH_ATTR uart0_interrupt_handler(uart_t* uart)
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{
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uint32_t status = READ_PERI_REG(UART_INT_ST(0));
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if (status & UART_RXFIFO_FULL_INT_ST)
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{
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while(true)
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{
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int rx_count = (READ_PERI_REG(UART_STATUS(0)) >> UART_RXFIFO_CNT_S) & UART_RXFIFO_CNT;
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if (!rx_count)
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break;
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/**
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* UART GPIOs
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*
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* UART0 TX: 1 or 2
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* UART0 RX: 3
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*
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* UART0 SWAP TX: 15
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* UART0 SWAP RX: 13
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*
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*
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* UART1 TX: 7 (NC) or 2
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* UART1 RX: 8 (NC)
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*
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* UART1 SWAP TX: 11 (NC)
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* UART1 SWAP RX: 6 (NC)
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*
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* NC = Not Connected to Module Pads --> No Access
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*
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*/
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while(rx_count--)
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{
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// ####################################################################################################
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// ####################################################################################################
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// ####################################################################################################
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HardwareSerial Serial(UART0);
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HardwareSerial Serial1(UART1);
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// ####################################################################################################
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// ####################################################################################################
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// ####################################################################################################
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void uart_interrupt_handler(uart_t* uart);
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void uart_wait_for_tx_fifo(uart_t* uart, size_t size_needed);
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size_t uart_get_tx_fifo_room(uart_t* uart);
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void uart_wait_for_transmit(uart_t* uart);
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void uart_transmit_char(uart_t* uart, char c);
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void uart_transmit(uart_t* uart, const char* buf, size_t size);
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void uart_flush(uart_t* uart);
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void uart_interrupt_enable(uart_t* uart);
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void uart_interrupt_disable(uart_t* uart);
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void uart_arm_tx_interrupt(uart_t* uart);
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void uart_disarm_tx_interrupt(uart_t* uart);
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void uart_set_baudrate(uart_t* uart, int baud_rate);
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int uart_get_baudrate(uart_t* uart);
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uart_t* uart_init(UARTnr_t uart_nr, int baudrate);
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void uart_uninit(uart_t* uart);
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void uart_swap(uart_t* uart);
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void uart_ignore_char(char c);
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void uart0_write_char(char c);
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void uart1_write_char(char c);
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void uart_set_debug(UARTnr_t uart_nr);
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UARTnr_t uart_get_debug();
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// ####################################################################################################
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// ####################################################################################################
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// ####################################################################################################
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void ICACHE_FLASH_ATTR uart_interrupt_handler(uart_t* uart) {
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// -------------- UART 0 --------------
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uint32_t status = READ_PERI_REG(UART_INT_ST(0));
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if(Serial.isRxEnabled()) {
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if(status & UART_RXFIFO_FULL_INT_ST) {
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while(true) {
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int rx_count = (READ_PERI_REG(UART_STATUS(0)) >> UART_RXFIFO_CNT_S) & UART_RXFIFO_CNT;
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if(!rx_count) break;
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while(rx_count--) {
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char c = READ_PERI_REG(UART_FIFO(0)) & 0xFF;
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Serial._rx_complete_irq(c);
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}
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}
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WRITE_PERI_REG(UART_INT_CLR(0), UART_RXFIFO_FULL_INT_CLR);
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}
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if (status & UART_TXFIFO_EMPTY_INT_ST)
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{
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}
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if(Serial.isTxEnabled()) {
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if(status & UART_TXFIFO_EMPTY_INT_ST) {
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WRITE_PERI_REG(UART_INT_CLR(0), UART_TXFIFO_EMPTY_INT_CLR);
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Serial._tx_empty_irq();
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}
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}
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}
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void ICACHE_FLASH_ATTR uart0_wait_for_tx_fifo(size_t size_needed)
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{
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while (true)
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{
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size_t tx_count = (READ_PERI_REG(UART_STATUS(0)) >> UART_TXFIFO_CNT_S) & UART_TXFIFO_CNT;
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if (tx_count <= (UART_TX_FIFO_SIZE - size_needed))
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break;
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// -------------- UART 1 --------------
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status = READ_PERI_REG(UART_INT_ST(1));
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if(Serial1.isRxEnabled()) {
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if(status & UART_RXFIFO_FULL_INT_ST) {
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while(true) {
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int rx_count = (READ_PERI_REG(UART_STATUS(1)) >> UART_RXFIFO_CNT_S) & UART_RXFIFO_CNT;
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if(!rx_count) break;
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while(rx_count--) {
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char c = READ_PERI_REG(UART_FIFO(1)) & 0xFF;
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Serial1._rx_complete_irq(c);
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}
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}
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WRITE_PERI_REG(UART_INT_CLR(1), UART_RXFIFO_FULL_INT_CLR);
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}
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}
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if(Serial1.isTxEnabled()) {
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status = READ_PERI_REG(UART_INT_ST(1));
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if(status & UART_TXFIFO_EMPTY_INT_ST) {
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WRITE_PERI_REG(UART_INT_CLR(1), UART_TXFIFO_EMPTY_INT_CLR);
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Serial1._tx_empty_irq();
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}
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}
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}
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size_t ICACHE_FLASH_ATTR uart0_get_tx_fifo_room()
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{
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return UART_TX_FIFO_SIZE - ((READ_PERI_REG(UART_STATUS(0)) >> UART_TXFIFO_CNT_S) & UART_TXFIFO_CNT);
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// ####################################################################################################
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void ICACHE_FLASH_ATTR uart_wait_for_tx_fifo(uart_t* uart, size_t size_needed) {
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if(uart->txEnabled) {
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while(true) {
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size_t tx_count = (READ_PERI_REG(UART_STATUS(uart->uart_nr)) >> UART_TXFIFO_CNT_S) & UART_TXFIFO_CNT;
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if(tx_count <= (UART_TX_FIFO_SIZE - size_needed)) break;
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}
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}
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}
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void ICACHE_FLASH_ATTR uart0_wait_for_transmit(uart_t* uart)
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{
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uart0_wait_for_tx_fifo(UART_TX_FIFO_SIZE);
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size_t ICACHE_FLASH_ATTR uart_get_tx_fifo_room(uart_t* uart) {
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if(uart->txEnabled) {
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return UART_TX_FIFO_SIZE - ((READ_PERI_REG(UART_STATUS(uart->uart_nr)) >> UART_TXFIFO_CNT_S) & UART_TXFIFO_CNT);
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}
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return 0;
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}
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void ICACHE_FLASH_ATTR uart0_transmit_char(uart_t* uart, char c)
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{
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WRITE_PERI_REG(UART_FIFO(0), c);
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void ICACHE_FLASH_ATTR uart_wait_for_transmit(uart_t* uart) {
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if(uart->txEnabled) {
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uart_wait_for_tx_fifo(uart, UART_TX_FIFO_SIZE);
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}
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}
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void ICACHE_FLASH_ATTR uart0_transmit(uart_t* uart, const char* buf, size_t size)
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{
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while (size)
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{
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void ICACHE_FLASH_ATTR uart_transmit_char(uart_t* uart, char c) {
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if(uart->txEnabled) {
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WRITE_PERI_REG(UART_FIFO(uart->uart_nr), c);
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}
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}
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void ICACHE_FLASH_ATTR uart_transmit(uart_t* uart, const char* buf, size_t size) {
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if(uart->txEnabled) {
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while(size) {
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size_t part_size = (size > UART_TX_FIFO_SIZE) ? UART_TX_FIFO_SIZE : size;
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size -= part_size;
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uart0_wait_for_tx_fifo(part_size);
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for(;part_size;--part_size, ++buf)
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WRITE_PERI_REG(UART_FIFO(0), *buf);
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uart_wait_for_tx_fifo(uart, part_size);
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for(; part_size; --part_size, ++buf)
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WRITE_PERI_REG(UART_FIFO(uart->uart_nr), *buf);
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}
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}
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}
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void ICACHE_FLASH_ATTR uart0_flush(uart_t* uart)
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{
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SET_PERI_REG_MASK(UART_CONF0(0), UART_RXFIFO_RST | UART_TXFIFO_RST);
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CLEAR_PERI_REG_MASK(UART_CONF0(0), UART_RXFIFO_RST | UART_TXFIFO_RST);
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void ICACHE_FLASH_ATTR uart_flush(uart_t* uart) {
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uint32_t tmp = 0x00000000;
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if(uart->rxEnabled) {
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tmp |= UART_RXFIFO_RST;
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}
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if(uart->txEnabled) {
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tmp |= UART_TXFIFO_RST;
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}
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SET_PERI_REG_MASK(UART_CONF0(uart->uart_nr), tmp);
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CLEAR_PERI_REG_MASK(UART_CONF0(uart->uart_nr), tmp);
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}
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void ICACHE_FLASH_ATTR uart0_interrupt_enable(uart_t* uart)
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{
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WRITE_PERI_REG(UART_INT_CLR(0), 0x1ff);
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ETS_UART_INTR_ATTACH(&uart0_interrupt_handler, uart);
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SET_PERI_REG_MASK(UART_INT_ENA(0), UART_RXFIFO_FULL_INT_ENA);
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void ICACHE_FLASH_ATTR uart_interrupt_enable(uart_t* uart) {
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WRITE_PERI_REG(UART_INT_CLR(uart->uart_nr), 0x1ff);
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ETS_UART_INTR_ATTACH(&uart_interrupt_handler, uart); // uart parameter is not osed in irq function!
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if(uart->rxEnabled) {
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SET_PERI_REG_MASK(UART_INT_ENA(uart->uart_nr), UART_RXFIFO_FULL_INT_ENA);
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}
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ETS_UART_INTR_ENABLE();
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}
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void ICACHE_FLASH_ATTR uart0_interrupt_disable(uart_t* uart)
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{
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CLEAR_PERI_REG_MASK(UART_INT_ENA(0), UART_RXFIFO_FULL_INT_ENA);
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ETS_UART_INTR_DISABLE();
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void ICACHE_FLASH_ATTR uart_interrupt_disable(uart_t* uart) {
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if(uart->rxEnabled) {
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CLEAR_PERI_REG_MASK(UART_INT_ENA(uart->uart_nr), UART_RXFIFO_FULL_INT_ENA);
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}
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if(uart->txEnabled) {
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CLEAR_PERI_REG_MASK(UART_INT_ENA(uart->uart_nr), UART_TXFIFO_EMPTY_INT_ENA);
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}
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//ETS_UART_INTR_DISABLE(); // never disable irq complete may its needed by the other Serial Interface!
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}
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void ICACHE_FLASH_ATTR uart0_arm_tx_interrupt()
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{
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SET_PERI_REG_MASK(UART_INT_ENA(0), UART_TXFIFO_EMPTY_INT_ENA);
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void ICACHE_FLASH_ATTR uart_arm_tx_interrupt(uart_t* uart) {
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if(uart->txEnabled) {
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SET_PERI_REG_MASK(UART_INT_ENA(uart->uart_nr), UART_TXFIFO_EMPTY_INT_ENA);
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}
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}
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void ICACHE_FLASH_ATTR uart0_disarm_tx_interrupt()
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{
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CLEAR_PERI_REG_MASK(UART_INT_ENA(0), UART_TXFIFO_EMPTY_INT_ENA);
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void ICACHE_FLASH_ATTR uart_disarm_tx_interrupt(uart_t* uart) {
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if(uart->txEnabled) {
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CLEAR_PERI_REG_MASK(UART_INT_ENA(uart->uart_nr), UART_TXFIFO_EMPTY_INT_ENA);
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}
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}
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void ICACHE_FLASH_ATTR uart0_set_baudrate(uart_t* uart, int baud_rate)
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{
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void ICACHE_FLASH_ATTR uart_set_baudrate(uart_t* uart, int baud_rate) {
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uart->baud_rate = baud_rate;
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uart_div_modify(0, UART_CLK_FREQ / (uart->baud_rate));
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uart_div_modify(uart->uart_nr, UART_CLK_FREQ / (uart->baud_rate));
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}
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int ICACHE_FLASH_ATTR uart0_get_baudrate(uart_t* uart)
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{
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int ICACHE_FLASH_ATTR uart_get_baudrate(uart_t* uart) {
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return uart->baud_rate;
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}
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uart_t* ICACHE_FLASH_ATTR uart0_init(int baudrate)
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{
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uart_t* uart = (uart_t*) os_malloc(sizeof(uart_t));
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uart_t* ICACHE_FLASH_ATTR uart_init(UARTnr_t uart_nr, int baudrate) {
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uint32_t conf1 = 0x00000000;
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uart_t* uart = (uart_t*) os_malloc(sizeof(uart_t));
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uart->uart_nr = uart_nr;
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switch(uart->uart_nr) {
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case UART0:
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PIN_PULLUP_DIS(PERIPHS_IO_MUX_U0TXD_U);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD);
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PIN_PULLUP_EN(PERIPHS_IO_MUX_U0RXD_U);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0RXD_U, FUNC_U0RXD);
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uart->rxEnabled = true;
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uart->txEnabled = true;
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uart->rxPin = 3;
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uart->txPin = 1;
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break;
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case UART1:
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PIN_PULLUP_DIS(PERIPHS_IO_MUX_GPIO2_U);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO2_U, FUNC_U1TXD_BK);
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uart->rxEnabled = false;
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uart->txEnabled = true;
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uart->rxPin = 255;
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uart->txPin = 2;
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break;
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case UART_NO:
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default:
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// big fail!
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break;
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}
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uart_set_baudrate(uart, baudrate);
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WRITE_PERI_REG(UART_CONF0(uart->uart_nr), 0x3 << UART_BIT_NUM_S); // 8n1
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uart0_set_baudrate(uart, baudrate);
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WRITE_PERI_REG(UART_CONF0(0), 0x3 << UART_BIT_NUM_S); // 8n1
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uart_flush(uart);
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uart_interrupt_enable(uart);
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uart0_flush(uart);
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uart0_interrupt_enable(uart);
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if(uart->rxEnabled) {
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conf1 |= ((0x01 & UART_RXFIFO_FULL_THRHD) << UART_RXFIFO_FULL_THRHD_S);
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}
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WRITE_PERI_REG(UART_CONF1(0), ((0x01 & UART_RXFIFO_FULL_THRHD) << UART_RXFIFO_FULL_THRHD_S) |
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((0x20 & UART_TXFIFO_EMPTY_THRHD) << UART_TXFIFO_EMPTY_THRHD_S));
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if(uart->txEnabled) {
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conf1 |= ((0x20 & UART_TXFIFO_EMPTY_THRHD) << UART_TXFIFO_EMPTY_THRHD_S);
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}
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WRITE_PERI_REG(UART_CONF1(uart->uart_nr), conf1);
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return uart;
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}
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void ICACHE_FLASH_ATTR uart0_uninit(uart_t* uart)
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{
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uart0_interrupt_disable(uart);
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// TODO: revert pin functions
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void ICACHE_FLASH_ATTR uart_uninit(uart_t* uart) {
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uart_interrupt_disable(uart);
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switch(uart->rxPin) {
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case 3:
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PIN_PULLUP_DIS(PERIPHS_IO_MUX_U0RXD_U);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0RXD_U, FUNC_GPIO3);
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break;
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case 13:
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PIN_PULLUP_DIS(PERIPHS_IO_MUX_MTCK_U);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, FUNC_GPIO13);
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break;
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}
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switch(uart->rxPin) {
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case 1:
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0TXD_U, FUNC_GPIO1);
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break;
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case 2:
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO2_U, FUNC_GPIO2);
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break;
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case 15:
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, FUNC_GPIO15);
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break;
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}
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pinMode(uart->rxPin , INPUT);
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pinMode(uart->txPin , INPUT);
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os_free(uart);
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||||
}
|
||||
|
||||
void ICACHE_FLASH_ATTR uart0_swap(uart_t* uart)
|
||||
{
|
||||
void ICACHE_FLASH_ATTR uart_swap(uart_t* uart) {
|
||||
switch(uart->uart_nr) {
|
||||
case UART0:
|
||||
if(uart->txPin == 1 && uart->rxPin == 3) {
|
||||
|
||||
PIN_PULLUP_DIS(PERIPHS_IO_MUX_MTCK_U);
|
||||
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, FUNC_UART0_CTS);
|
||||
|
||||
PIN_PULLUP_EN(PERIPHS_IO_MUX_MTDO_U);
|
||||
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, FUNC_UART0_RTS);
|
||||
|
||||
//SWAP PIN : U0TXD<==>U0RTS(MTDO, GPIO15) , U0RXD<==>U0CTS(MTCK, GPIO13)
|
||||
SET_PERI_REG_MASK(0x3ff00028 , BIT2);
|
||||
PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0TXD_U, FUNC_GPIO1);
|
||||
SET_PERI_REG_MASK(0x3ff00028, BIT2);
|
||||
|
||||
PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0RXD_U, FUNC_GPIO3);
|
||||
PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0TXD_U, FUNC_GPIO1);
|
||||
|
||||
|
||||
pinMode(uart->rxPin, INPUT);
|
||||
pinMode(uart->txPin, INPUT);
|
||||
|
||||
uart->rxPin = 13;
|
||||
uart->txPin = 15;
|
||||
|
||||
} else {
|
||||
PIN_PULLUP_DIS(PERIPHS_IO_MUX_U0TXD_U);
|
||||
PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD);
|
||||
|
||||
PIN_PULLUP_EN(PERIPHS_IO_MUX_U0RXD_U);
|
||||
PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0RXD_U, FUNC_U0RXD);
|
||||
|
||||
CLEAR_PERI_REG_MASK(0x3ff00028, BIT2);
|
||||
|
||||
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, FUNC_GPIO13);
|
||||
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, FUNC_GPIO15);
|
||||
|
||||
|
||||
pinMode(uart->rxPin, INPUT);
|
||||
pinMode(uart->txPin, INPUT);
|
||||
uart->rxPin = 3;
|
||||
uart->txPin = 1;
|
||||
}
|
||||
|
||||
break;
|
||||
case UART1:
|
||||
// current no swap possible! see GPIO pins used by UART
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void ICACHE_FLASH_ATTR
|
||||
uart_ignore_char(char c)
|
||||
{
|
||||
// ####################################################################################################
|
||||
// ####################################################################################################
|
||||
// ####################################################################################################
|
||||
|
||||
void ICACHE_FLASH_ATTR uart_ignore_char(char c) {
|
||||
}
|
||||
|
||||
void ICACHE_FLASH_ATTR
|
||||
uart_write_char(char c)
|
||||
{
|
||||
if (c == '\n')
|
||||
void ICACHE_FLASH_ATTR uart0_write_char(char c) {
|
||||
if(c == '\n') {
|
||||
WRITE_PERI_REG(UART_FIFO(0), '\r');
|
||||
|
||||
}
|
||||
WRITE_PERI_REG(UART_FIFO(0), c);
|
||||
}
|
||||
|
||||
bool s_uart_debug_enabled = true;
|
||||
void ICACHE_FLASH_ATTR uart_set_debug(bool enabled)
|
||||
{
|
||||
s_uart_debug_enabled = enabled;
|
||||
if (enabled)
|
||||
{
|
||||
system_set_os_print(1);
|
||||
ets_install_putc1((void *)&uart_write_char);
|
||||
void ICACHE_FLASH_ATTR uart1_write_char(char c) {
|
||||
if(c == '\n') {
|
||||
WRITE_PERI_REG(UART_FIFO(1), '\r');
|
||||
}
|
||||
else
|
||||
ets_install_putc1((void *)&uart_ignore_char);
|
||||
WRITE_PERI_REG(UART_FIFO(1), c);
|
||||
}
|
||||
|
||||
bool ICACHE_FLASH_ATTR uart_get_debug()
|
||||
{
|
||||
return s_uart_debug_enabled;
|
||||
static UARTnr_t s_uart_debug_nr = UART_NO;
|
||||
void ICACHE_FLASH_ATTR uart_set_debug(UARTnr_t uart_nr) {
|
||||
s_uart_debug_nr = uart_nr;
|
||||
switch(s_uart_debug_nr) {
|
||||
case UART0:
|
||||
system_set_os_print(1);
|
||||
ets_install_putc1((void *) &uart0_write_char);
|
||||
break;
|
||||
case UART1:
|
||||
system_set_os_print(1);
|
||||
ets_install_putc1((void *) &uart1_write_char);
|
||||
break;
|
||||
case UART_NO:
|
||||
default:
|
||||
system_set_os_print(0);
|
||||
ets_install_putc1((void *) &uart_ignore_char);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
ICACHE_FLASH_ATTR HardwareSerial::HardwareSerial() :
|
||||
_uart(0), _rx_buffer(0), _tx_buffer(0)
|
||||
{
|
||||
UARTnr_t ICACHE_FLASH_ATTR uart_get_debug() {
|
||||
return s_uart_debug_nr;
|
||||
}
|
||||
|
||||
void ICACHE_FLASH_ATTR HardwareSerial::begin(unsigned long baud, byte config)
|
||||
{
|
||||
// ####################################################################################################
|
||||
// ####################################################################################################
|
||||
// ####################################################################################################
|
||||
|
||||
ICACHE_FLASH_ATTR HardwareSerial::HardwareSerial(UARTnr_t uart_nr) :
|
||||
_uart(0), _tx_buffer(0), _rx_buffer(0), _written(false) {
|
||||
_uart_nr = uart_nr;
|
||||
}
|
||||
|
||||
void ICACHE_FLASH_ATTR HardwareSerial::begin(unsigned long baud, byte config) {
|
||||
|
||||
// disable debug for this interface
|
||||
if(uart_get_debug() == _uart_nr) {
|
||||
uart_set_debug(UART_NO);
|
||||
}
|
||||
|
||||
_uart = uart_init(_uart_nr, baud);
|
||||
|
||||
if(_uart->rxEnabled) {
|
||||
_rx_buffer = new cbuf(SERIAL_RX_BUFFER_SIZE);
|
||||
}
|
||||
if(_uart->txEnabled) {
|
||||
_tx_buffer = new cbuf(SERIAL_TX_BUFFER_SIZE);
|
||||
uart_set_debug(false);
|
||||
_uart = uart0_init(baud);
|
||||
}
|
||||
_written = false;
|
||||
delay(1);
|
||||
}
|
||||
|
||||
void ICACHE_FLASH_ATTR HardwareSerial::end()
|
||||
{
|
||||
uart0_uninit(_uart);
|
||||
void ICACHE_FLASH_ATTR HardwareSerial::end() {
|
||||
uart_uninit(_uart);
|
||||
delete _rx_buffer;
|
||||
delete _tx_buffer;
|
||||
_uart = 0;
|
||||
@ -257,65 +468,86 @@ void ICACHE_FLASH_ATTR HardwareSerial::end()
|
||||
_tx_buffer = 0;
|
||||
}
|
||||
|
||||
void ICACHE_FLASH_ATTR HardwareSerial::swap()
|
||||
{
|
||||
uart0_swap(_uart);
|
||||
pinMode(1, INPUT);
|
||||
pinMode(3, INPUT);
|
||||
void ICACHE_FLASH_ATTR HardwareSerial::swap() {
|
||||
uart_swap(_uart);
|
||||
}
|
||||
|
||||
void ICACHE_FLASH_ATTR HardwareSerial::setDebugOutput(bool en)
|
||||
{
|
||||
uart_set_debug(en);
|
||||
void ICACHE_FLASH_ATTR HardwareSerial::setDebugOutput(bool en) {
|
||||
if(en) {
|
||||
uart_set_debug(_uart->uart_nr);
|
||||
} else {
|
||||
// disable debug for this interface
|
||||
if(uart_get_debug() == _uart_nr) {
|
||||
uart_set_debug(UART_NO);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
int ICACHE_FLASH_ATTR HardwareSerial::available(void)
|
||||
{
|
||||
bool ICACHE_FLASH_ATTR HardwareSerial::isTxEnabled(void) {
|
||||
if(_uart == 0) return false;
|
||||
return _uart->txEnabled;
|
||||
}
|
||||
|
||||
bool ICACHE_FLASH_ATTR HardwareSerial::isRxEnabled(void) {
|
||||
if(_uart == 0) return false;
|
||||
return _uart->rxEnabled;
|
||||
}
|
||||
|
||||
int ICACHE_FLASH_ATTR HardwareSerial::available(void) {
|
||||
if(_uart->rxEnabled) {
|
||||
return static_cast<int>(_rx_buffer->getSize());
|
||||
} else {
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
int ICACHE_FLASH_ATTR HardwareSerial::peek(void)
|
||||
{
|
||||
int ICACHE_FLASH_ATTR HardwareSerial::peek(void) {
|
||||
if(_uart->rxEnabled) {
|
||||
return _rx_buffer->peek();
|
||||
} else {
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
int ICACHE_FLASH_ATTR HardwareSerial::read(void)
|
||||
{
|
||||
int ICACHE_FLASH_ATTR HardwareSerial::read(void) {
|
||||
if(_uart->rxEnabled) {
|
||||
return _rx_buffer->read();
|
||||
} else {
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
int ICACHE_FLASH_ATTR HardwareSerial::availableForWrite(void)
|
||||
{
|
||||
int ICACHE_FLASH_ATTR HardwareSerial::availableForWrite(void) {
|
||||
if(_uart->txEnabled) {
|
||||
return static_cast<int>(_tx_buffer->room());
|
||||
} else {
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
void ICACHE_FLASH_ATTR HardwareSerial::flush()
|
||||
{
|
||||
if (!_written)
|
||||
return;
|
||||
void ICACHE_FLASH_ATTR HardwareSerial::flush() {
|
||||
if(!_uart->txEnabled) return;
|
||||
if(!_written) return;
|
||||
|
||||
while (_tx_buffer->getSize() || uart0_get_tx_fifo_room() < UART_TX_FIFO_SIZE)
|
||||
while(_tx_buffer->getSize() || uart_get_tx_fifo_room(_uart) < UART_TX_FIFO_SIZE)
|
||||
yield();
|
||||
|
||||
_written = false;
|
||||
}
|
||||
|
||||
size_t ICACHE_FLASH_ATTR HardwareSerial::write(uint8_t c)
|
||||
{
|
||||
size_t ICACHE_FLASH_ATTR HardwareSerial::write(uint8_t c) {
|
||||
if(!_uart->txEnabled) return 0;
|
||||
_written = true;
|
||||
size_t room = uart0_get_tx_fifo_room();
|
||||
if (room > 0 && _tx_buffer->empty())
|
||||
{
|
||||
uart0_transmit_char(_uart, c);
|
||||
if (room < 10)
|
||||
{
|
||||
uart0_arm_tx_interrupt();
|
||||
size_t room = uart_get_tx_fifo_room(_uart);
|
||||
if(room > 0 && _tx_buffer->empty()) {
|
||||
uart_transmit_char(_uart, c);
|
||||
if(room < 10) {
|
||||
uart_arm_tx_interrupt(_uart);
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
while (_tx_buffer->room() == 0)
|
||||
{
|
||||
while(_tx_buffer->room() == 0) {
|
||||
yield();
|
||||
}
|
||||
|
||||
@ -323,30 +555,24 @@ size_t ICACHE_FLASH_ATTR HardwareSerial::write(uint8_t c)
|
||||
return 1;
|
||||
}
|
||||
|
||||
ICACHE_FLASH_ATTR HardwareSerial::operator bool() const
|
||||
{
|
||||
ICACHE_FLASH_ATTR HardwareSerial::operator bool() const {
|
||||
return _uart != 0;
|
||||
}
|
||||
|
||||
void ICACHE_FLASH_ATTR HardwareSerial::_rx_complete_irq(char c)
|
||||
{
|
||||
void ICACHE_FLASH_ATTR HardwareSerial::_rx_complete_irq(char c) {
|
||||
_rx_buffer->write(c);
|
||||
}
|
||||
|
||||
void ICACHE_FLASH_ATTR HardwareSerial::_tx_empty_irq(void)
|
||||
{
|
||||
void ICACHE_FLASH_ATTR HardwareSerial::_tx_empty_irq(void) {
|
||||
size_t queued = _tx_buffer->getSize();
|
||||
if (!queued)
|
||||
{
|
||||
uart0_disarm_tx_interrupt();
|
||||
if(!queued) {
|
||||
uart_disarm_tx_interrupt(_uart);
|
||||
return;
|
||||
}
|
||||
|
||||
size_t room = uart0_get_tx_fifo_room();
|
||||
size_t room = uart_get_tx_fifo_room(_uart);
|
||||
int n = static_cast<int>((queued < room) ? queued : room);
|
||||
while (n--)
|
||||
{
|
||||
uart0_transmit_char(_uart, _tx_buffer->read());
|
||||
while(n--) {
|
||||
uart_transmit_char(_uart, _tx_buffer->read());
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -20,7 +20,8 @@
|
||||
Modified 14 August 2012 by Alarus
|
||||
Modified 3 December 2013 by Matthijs Kooijman
|
||||
Modified 18 December 2014 by Ivan Grokhotkov (esp8266 platform support)
|
||||
*/
|
||||
Modified 31 March 2015 by Markus Sattler (rewrite the code for UART0 + UART1 support in ESP8266)
|
||||
*/
|
||||
|
||||
#ifndef HardwareSerial_h
|
||||
#define HardwareSerial_h
|
||||
@ -59,14 +60,29 @@
|
||||
// #define SERIAL_8O2 0x3E
|
||||
|
||||
class cbuf;
|
||||
typedef struct uart_ uart_t;
|
||||
|
||||
class HardwareSerial : public Stream
|
||||
{
|
||||
public:
|
||||
HardwareSerial();
|
||||
typedef enum {
|
||||
UART0 = 0,
|
||||
UART1 = 1,
|
||||
UART_NO = 0xFF
|
||||
} UARTnr_t;
|
||||
|
||||
void begin(unsigned long baud) { begin(baud, 0); }
|
||||
typedef struct {
|
||||
UARTnr_t uart_nr;
|
||||
int baud_rate;
|
||||
bool rxEnabled;
|
||||
bool txEnabled;
|
||||
uint8_t rxPin;
|
||||
uint8_t txPin;
|
||||
} uart_t;
|
||||
|
||||
class HardwareSerial: public Stream {
|
||||
public:
|
||||
HardwareSerial(UARTnr_t uart_nr);
|
||||
|
||||
void begin(unsigned long baud) {
|
||||
begin(baud, 0);
|
||||
}
|
||||
void begin(unsigned long, uint8_t);
|
||||
void end();
|
||||
void swap(); //use GPIO13 and GPIO15 as RX and TX
|
||||
@ -76,21 +92,32 @@ public:
|
||||
int availableForWrite(void);
|
||||
void flush(void) override;
|
||||
size_t write(uint8_t) override;
|
||||
inline size_t write(unsigned long n) { return write((uint8_t)n); }
|
||||
inline size_t write(long n) { return write((uint8_t)n); }
|
||||
inline size_t write(unsigned int n) { return write((uint8_t)n); }
|
||||
inline size_t write(int n) { return write((uint8_t)n); }
|
||||
inline size_t write(unsigned long n) {
|
||||
return write((uint8_t) n);
|
||||
}
|
||||
inline size_t write(long n) {
|
||||
return write((uint8_t) n);
|
||||
}
|
||||
inline size_t write(unsigned int n) {
|
||||
return write((uint8_t) n);
|
||||
}
|
||||
inline size_t write(int n) {
|
||||
return write((uint8_t) n);
|
||||
}
|
||||
using Print::write; // pull in write(str) and write(buf, size) from Print
|
||||
operator bool() const;
|
||||
|
||||
void setDebugOutput(bool);
|
||||
bool isTxEnabled(void);
|
||||
bool isRxEnabled(void);
|
||||
|
||||
protected:
|
||||
friend void uart0_interrupt_handler(uart_t* uart);
|
||||
protected:
|
||||
friend void uart_interrupt_handler(uart_t* uart);
|
||||
void _rx_complete_irq(char c);
|
||||
void _tx_empty_irq(void);
|
||||
|
||||
protected:
|
||||
protected:
|
||||
UARTnr_t _uart_nr;
|
||||
uart_t* _uart;
|
||||
cbuf* _tx_buffer;
|
||||
cbuf* _rx_buffer;
|
||||
@ -98,5 +125,6 @@ protected:
|
||||
};
|
||||
|
||||
extern HardwareSerial Serial;
|
||||
extern HardwareSerial Serial1;
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user