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Xmc flash 2 (#7317)
* Remove unnecessary XMC support from eboot eboot is always run with the flash access speed set to 20MHz, so there is no need for special treatment of XMC chips. * After eboot copies the new firmware into place, verify the copy. If the data written to flash is as expected, the line cmp:0 will be displayed after the usual @cp:0 from eboot. * Disable interrupts during the precached part of _SPICommand() For some reason this was an issue during the reboot after an OTA update.
This commit is contained in:
Mike Nix
GitHub
parent
0deb87483e
commit
51daecc236
@ -12,7 +12,6 @@
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#include <string.h>
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#include "flash.h"
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#include "eboot_command.h"
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#include "spi_vendors.h"
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#include <uzlib.h>
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extern unsigned char _gzip_dict;
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@ -115,10 +114,12 @@ int uzlib_flash_read_cb(struct uzlib_uncomp *m)
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}
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unsigned char gzip_dict[32768];
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uint8_t buffer2[FLASH_SECTOR_SIZE]; // no room for this on the stack
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int copy_raw(const uint32_t src_addr,
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const uint32_t dst_addr,
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const uint32_t size)
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const uint32_t size,
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const bool verify)
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{
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// require regions to be aligned
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if ((src_addr & 0xfff) != 0 ||
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@ -158,8 +159,10 @@ int copy_raw(const uint32_t src_addr,
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gzip = true;
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}
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while (left > 0) {
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if (SPIEraseSector(daddr/buffer_size)) {
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return 2;
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if (!verify) {
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if (SPIEraseSector(daddr/buffer_size)) {
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return 2;
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}
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}
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if (!gzip) {
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if (SPIRead(saddr, buffer, buffer_size)) {
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@ -179,8 +182,17 @@ int copy_raw(const uint32_t src_addr,
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buffer[i] = 0xff;
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}
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}
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if (SPIWrite(daddr, buffer, buffer_size)) {
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return 4;
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if (verify) {
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if (SPIRead(daddr, buffer2, buffer_size)) {
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return 4;
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}
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if (memcmp(buffer, buffer2, buffer_size)) {
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return 9;
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}
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} else {
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if (SPIWrite(daddr, buffer, buffer_size)) {
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return 4;
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}
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}
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saddr += buffer_size;
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daddr += buffer_size;
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@ -190,29 +202,6 @@ int copy_raw(const uint32_t src_addr,
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return 0;
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}
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//#define XMC_SUPPORT
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#ifdef XMC_SUPPORT
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// Define a few SPI0 registers we need access to
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#define ESP8266_REG(addr) *((volatile uint32_t *)(0x60000000+(addr)))
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#define SPI0CMD ESP8266_REG(0x200)
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#define SPI0CLK ESP8266_REG(0x218)
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#define SPI0C ESP8266_REG(0x208)
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#define SPI0W0 ESP8266_REG(0x240)
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#define SPICMDRDID (1 << 28)
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/* spi_flash_get_id()
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Returns the flash chip ID - same as the SDK function.
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We need our own version as the SDK isn't available here.
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*/
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uint32_t __attribute__((noinline)) spi_flash_get_id() {
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SPI0W0=0;
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SPI0CMD=SPICMDRDID;
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while (SPI0CMD) {}
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return SPI0W0;
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}
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#endif // XMC_SUPPORT
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int main()
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{
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int res = 9;
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@ -235,47 +224,20 @@ int main()
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if (cmd.action == ACTION_COPY_RAW) {
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ets_putc('c'); ets_putc('p'); ets_putc(':');
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#ifdef XMC_SUPPORT
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// save the flash access speed registers
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uint32_t spi0clk = SPI0CLK;
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uint32_t spi0c = SPI0C;
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uint32_t vendor = spi_flash_get_id() & 0x000000ff;
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if (vendor == SPI_FLASH_VENDOR_XMC) {
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uint32_t flashinfo=0;
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if (SPIRead(0, &flashinfo, 4)) {
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// failed to read the configured flash speed.
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// Do not change anything,
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} else {
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// select an appropriate flash speed
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// Register values are those used by ROM
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switch ((flashinfo >> 24) & 0x0f) {
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case 0x0: // 40MHz, slow to 20
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case 0x1: // 26MHz, slow to 20
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SPI0CLK = 0x00003043;
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SPI0C = 0x00EAA313;
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break;
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case 0x2: // 20MHz, no change
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break;
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case 0xf: // 80MHz, slow to 26
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SPI0CLK = 0x00002002;
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SPI0C = 0x00EAA202;
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break;
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default:
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break;
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}
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}
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}
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#endif // XMC_SUPPORT
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ets_wdt_disable();
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res = copy_raw(cmd.args[0], cmd.args[1], cmd.args[2]);
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res = copy_raw(cmd.args[0], cmd.args[1], cmd.args[2], false);
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ets_wdt_enable();
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#ifdef XMC_SUPPORT
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// restore the saved flash access speed registers
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SPI0CLK = spi0clk;
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SPI0C = spi0c;
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#endif
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ets_putc('0'+res); ets_putc('\n');
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// Verify the copy
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ets_putc('c'); ets_putc('m'); ets_putc('p'); ets_putc(':');
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if (res == 0) {
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ets_wdt_disable();
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res = copy_raw(cmd.args[0], cmd.args[1], cmd.args[2], true);
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ets_wdt_enable();
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}
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ets_putc('0'+res); ets_putc('\n');
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if (res == 0) {
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cmd.action = ACTION_LOAD_APP;
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Binary file not shown.
@ -52,7 +52,7 @@ static SpiOpResult PRECACHE_ATTR
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_SPICommand(volatile uint32_t spiIfNum,
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uint32_t spic,uint32_t spiu,uint32_t spiu1,uint32_t spiu2,
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uint32_t *data,uint32_t writeWords,uint32_t readWords)
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{
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{
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if (spiIfNum>1)
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return SPI_RESULT_ERR;
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@ -69,8 +69,11 @@ _SPICommand(volatile uint32_t spiIfNum,
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volatile SpiFlashChip *fchip=flashchip;
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volatile uint32_t spicmdusr=SPICMDUSR;
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uint32_t saved_ps=0;
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if (!spiIfNum) {
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// Only need to precache when using SPI0
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// Only need to disable interrupts and precache when using SPI0
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saved_ps = xt_rsil(15);
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PRECACHE_START();
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Wait_SPI_Idlep((SpiFlashChip *)fchip);
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}
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@ -116,6 +119,9 @@ _SPICommand(volatile uint32_t spiIfNum,
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SPIREG(SPI0C) = oldSPI0C;
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PRECACHE_END();
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if (!spiIfNum) {
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xt_wsr_ps(saved_ps);
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}
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return (timeout>0 ? SPI_RESULT_OK : SPI_RESULT_TIMEOUT);
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}
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