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Xmc flash 2 (#7317)

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* Remove unnecessary XMC support from eboot

eboot is always run with the flash access speed set to 20MHz, so
there is no need for special treatment of XMC chips.

* After eboot copies the new firmware into place, verify the copy.

If the data written to flash is as expected, the line cmp:0 will be displayed
after the usual @cp:0 from eboot.

* Disable interrupts during the precached part of _SPICommand()

For some reason this was an issue during the reboot after an OTA update.
This commit is contained in:
Mike Nix
2020-05-27 08:04:49 +08:00
committed by GitHub
parent 0deb87483e
commit 51daecc236
3 changed files with 38 additions and 70 deletions
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10
cores/esp8266/core_esp8266_spi_utils.cpp
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@ -52,7 +52,7 @@ static SpiOpResult PRECACHE_ATTR
_SPICommand(volatile uint32_t spiIfNum,
uint32_t spic,uint32_t spiu,uint32_t spiu1,uint32_t spiu2,
uint32_t *data,uint32_t writeWords,uint32_t readWords)
{
{
if (spiIfNum>1)
return SPI_RESULT_ERR;
@ -69,8 +69,11 @@ _SPICommand(volatile uint32_t spiIfNum,
volatile SpiFlashChip *fchip=flashchip;
volatile uint32_t spicmdusr=SPICMDUSR;
uint32_t saved_ps=0;
if (!spiIfNum) {
// Only need to precache when using SPI0
// Only need to disable interrupts and precache when using SPI0
saved_ps = xt_rsil(15);
PRECACHE_START();
Wait_SPI_Idlep((SpiFlashChip *)fchip);
}
@ -116,6 +119,9 @@ _SPICommand(volatile uint32_t spiIfNum,
SPIREG(SPI0C) = oldSPI0C;
PRECACHE_END();
if (!spiIfNum) {
xt_wsr_ps(saved_ps);
}
return (timeout>0 ? SPI_RESULT_OK : SPI_RESULT_TIMEOUT);
}