mirror of
https://github.com/esp8266/Arduino.git
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Add eboot
This commit is contained in:
parent
9db67ec7b0
commit
48e0d44860
26
bootloaders/eboot/LICENSE
Normal file
26
bootloaders/eboot/LICENSE
Normal file
@ -0,0 +1,26 @@
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Copyright (c) 2015 Ivan Grokhotkov
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. The name of the authors may not be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
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SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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Authors: Ivan Grokhotkov
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50
bootloaders/eboot/Makefile
Normal file
50
bootloaders/eboot/Makefile
Normal file
@ -0,0 +1,50 @@
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XTENSA_TOOCHAIN ?=
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BIN_DIR := ./
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TARGET_DIR := ./
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TARGET_OBJ_FILES := \
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eboot_debug.o \
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TARGET_OBJ_PATHS := $(addprefix $(TARGET_DIR)/,$(TARGET_OBJ_FILES))
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CC := $(XTENSA_TOOCHAIN)xtensa-lx106-elf-gcc
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CXX := $(XTENSA_TOOCHAIN)xtensa-lx106-elf-g++
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AR := $(XTENSA_TOOCHAIN)xtensa-lx106-elf-ar
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LD := $(XTENSA_TOOCHAIN)xtensa-lx106-elf-gcc
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OBJDUMP := $(XTENSA_TOOCHAIN)xtensa-lx106-elf-objdump
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CFLAGS += -std=gnu99
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CFLAGS += -O0 -g -Wpointer-arith -Wno-implicit-function-declaration -Wl,-EL -fno-inline-functions -nostdlib -mlongcalls -mno-text-section-literals
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LDFLAGS += -nostdlib -Wl,--no-check-sections -umain
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LD_SCRIPT := -Teboot.ld
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APP_OUT:= eboot.elf
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APP_AR := eboot.a
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APP_FW := eboot.bin
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all: $(APP_FW)
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$(APP_AR): $(TARGET_OBJ_PATHS)
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$(AR) cru $@ $^
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$(APP_OUT): $(APP_AR)
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$(LD) $(LD_SCRIPT) $(LDFLAGS) -Wl,--start-group -Wl,--whole-archive $(APP_AR) -Wl,--end-group -o $@
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$(APP_FW): $(APP_OUT)
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$(ESPTOOL) -vvv -eo $(APP_OUT) -bo $@ -bs .text -bs .data -bs .rodata -bc -ec || true
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clean:
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rm -f *.o
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rm -f $(APP_AR)
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rm -f $(APP_OUT)
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.PHONY: all clean default
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86
bootloaders/eboot/eboot.c
Normal file
86
bootloaders/eboot/eboot.c
Normal file
@ -0,0 +1,86 @@
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/* Copyright (c) 2015 Ivan Grokhotkov. All rights reserved.
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* This file is part of eboot bootloader.
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*
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* Redistribution and use is permitted according to the conditions of the
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* 3-clause BSD license to be found in the LICENSE file.
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*/
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#include <stddef.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include "eboot.h"
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extern void* flashchip;
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#define SWRST do { (*((volatile uint32_t*) 0x60000700)) |= 0x80000000; } while(0);
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int load_app_from_flash_raw(const uint32_t flash_addr)
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{
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image_header_t image_header;
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uint32_t pos = flash_addr + APP_START_OFFSET;
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if (SPIRead(pos, &image_header, sizeof(image_header))) {
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return 1;
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}
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pos += sizeof(image_header);
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for (uint32_t section_index = 0;
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section_index < image_header.num_segments;
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++section_index)
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{
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section_header_t section_header = {0};
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if (SPIRead(pos, §ion_header, sizeof(section_header))) {
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return 2;
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}
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pos += sizeof(section_header);
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const uint32_t address = section_header.address;
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bool load = false;
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if (address < 0x40000000) {
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load = true;
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}
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if (address >= 0x40100000 && address < 0x40108000) {
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load = true;
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}
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if (address >= 0x60000000) {
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load = true;
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}
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if (!load) {
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pos += section_header.size;
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continue;
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}
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if (SPIRead(pos, (void*)address, section_header.size))
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return 3;
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pos += section_header.size;
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}
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register uint32_t sp asm("a1") = 0x3ffffff0;
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register uint32_t pc asm("a3") = image_header.entry;
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__asm__ __volatile__ ("jx a3");
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return 0;
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}
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void main()
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{
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int res = load_app_from_flash_raw(0);
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if (res) {
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ets_putc('\n');
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ets_putc('#');
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ets_putc('0' + res);
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ets_putc('\n');
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SWRST;
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}
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while(true){}
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}
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BIN
bootloaders/eboot/eboot.elf
Executable file
BIN
bootloaders/eboot/eboot.elf
Executable file
Binary file not shown.
41
bootloaders/eboot/eboot.h
Normal file
41
bootloaders/eboot/eboot.h
Normal file
@ -0,0 +1,41 @@
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/* Copyright (c) 2015 Ivan Grokhotkov. All rights reserved.
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* This file is part of eboot bootloader.
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*
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* Redistribution and use is permitted according to the conditions of the
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* 3-clause BSD license to be found in the LICENSE file.
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*/
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#ifndef EBOOT_H
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#define EBOOT_H
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int SPIEraseBlock(uint32_t block);
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int SPIEraseSector(uint32_t sector);
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int SPIRead(uint32_t addr, void *dest, size_t size);
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int SPIWrite(uint32_t addr, void *src, size_t size);
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#define APP_START_OFFSET 0x1000
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typedef struct {
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unsigned char magic;
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unsigned char num_segments;
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/* SPI Flash Interface (0 = QIO, 1 = QOUT, 2 = DIO, 0x3 = DOUT) */
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unsigned char flash_mode;
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/* High four bits: 0 = 512K, 1 = 256K, 2 = 1M, 3 = 2M, 4 = 4M,
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Low four bits: 0 = 40MHz, 1= 26MHz, 2 = 20MHz, 0xf = 80MHz */
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unsigned char flash_size_freq;
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uint32_t entry;
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} image_header_t;
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typedef struct {
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uint32_t address;
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uint32_t size;
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} section_header_t;
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#endif //EBOOT_H
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176
bootloaders/eboot/eboot.ld
Normal file
176
bootloaders/eboot/eboot.ld
Normal file
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/* This linker script generated from xt-genldscripts.tpp for LSP . */
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/* Linker Script for ld -N */
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MEMORY
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{
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dport0_0_seg : org = 0x3FF00000, len = 0x10
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dram0_0_seg : org = 0x3FFE8000, len = 0x14000
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iram1_0_seg : org = 0x4010f800, len = 0x800
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irom0_0_seg : org = 0x40240000, len = 0x32000
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}
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PHDRS
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{
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dport0_0_phdr PT_LOAD;
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dram0_0_phdr PT_LOAD;
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dram0_0_bss_phdr PT_LOAD;
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iram1_0_phdr PT_LOAD;
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irom0_0_phdr PT_LOAD;
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}
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/* Default entry point: */
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ENTRY(main)
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PROVIDE(_memmap_vecbase_reset = 0x40000000);
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/* Various memory-map dependent cache attribute settings: */
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_memmap_cacheattr_wb_base = 0x00000110;
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_memmap_cacheattr_wt_base = 0x00000110;
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_memmap_cacheattr_bp_base = 0x00000220;
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_memmap_cacheattr_unused_mask = 0xFFFFF00F;
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_memmap_cacheattr_wb_trapnull = 0x2222211F;
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_memmap_cacheattr_wba_trapnull = 0x2222211F;
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_memmap_cacheattr_wbna_trapnull = 0x2222211F;
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_memmap_cacheattr_wt_trapnull = 0x2222211F;
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_memmap_cacheattr_bp_trapnull = 0x2222222F;
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_memmap_cacheattr_wb_strict = 0xFFFFF11F;
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_memmap_cacheattr_wt_strict = 0xFFFFF11F;
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_memmap_cacheattr_bp_strict = 0xFFFFF22F;
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_memmap_cacheattr_wb_allvalid = 0x22222112;
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_memmap_cacheattr_wt_allvalid = 0x22222112;
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_memmap_cacheattr_bp_allvalid = 0x22222222;
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PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
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SECTIONS
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{
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.dport0.rodata : ALIGN(4)
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{
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_dport0_rodata_start = ABSOLUTE(.);
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*(.dport0.rodata)
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*(.dport.rodata)
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_dport0_rodata_end = ABSOLUTE(.);
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} >dport0_0_seg :dport0_0_phdr
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.dport0.literal : ALIGN(4)
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{
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_dport0_literal_start = ABSOLUTE(.);
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*(.dport0.literal)
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*(.dport.literal)
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_dport0_literal_end = ABSOLUTE(.);
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||||
} >dport0_0_seg :dport0_0_phdr
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.dport0.data : ALIGN(4)
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||||
{
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||||
_dport0_data_start = ABSOLUTE(.);
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*(.dport0.data)
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*(.dport.data)
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_dport0_data_end = ABSOLUTE(.);
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} >dport0_0_seg :dport0_0_phdr
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||||
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.data : ALIGN(4)
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{
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_heap_start = ABSOLUTE(.);
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/* _stack_sentry = ALIGN(0x8); */
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} >dram0_0_seg :dram0_0_bss_phdr
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/* __stack = 0x3ffc8000; */
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||||
|
||||
.text : ALIGN(4)
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||||
{
|
||||
_stext = .;
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||||
_text_start = ABSOLUTE(.);
|
||||
*(.entry.text)
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||||
*(.init.literal)
|
||||
*(.init)
|
||||
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
|
||||
*(.fini.literal)
|
||||
*(.fini)
|
||||
*(.gnu.version)
|
||||
_text_end = ABSOLUTE(.);
|
||||
_etext = .;
|
||||
. = ALIGN (8);
|
||||
_data_start = ABSOLUTE(.);
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
*(.sdata2)
|
||||
*(.sdata2.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
*(.jcr)
|
||||
_data_end = ABSOLUTE(.);
|
||||
. = ALIGN (8);
|
||||
_rodata_start = ABSOLUTE(.);
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.rodata1)
|
||||
__XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
|
||||
*(.xt_except_table)
|
||||
*(.gcc_except_table)
|
||||
*(.gnu.linkonce.e.*)
|
||||
*(.gnu.version_r)
|
||||
*(.eh_frame)
|
||||
/* C++ constructor and destructor tables, properly ordered: */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
/* C++ exception handlers table: */
|
||||
__XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
|
||||
*(.xt_except_desc)
|
||||
*(.gnu.linkonce.h.*)
|
||||
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
|
||||
*(.xt_except_desc_end)
|
||||
*(.dynamic)
|
||||
*(.gnu.version_d)
|
||||
. = ALIGN(4); /* this table MUST be 4-byte aligned */
|
||||
_bss_table_start = ABSOLUTE(.);
|
||||
LONG(_bss_start)
|
||||
LONG(_bss_end)
|
||||
_bss_table_end = ABSOLUTE(.);
|
||||
_rodata_end = ABSOLUTE(.);
|
||||
|
||||
. = ALIGN (8);
|
||||
_bss_start = ABSOLUTE(.);
|
||||
*(.dynsbss)
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
*(.sbss2)
|
||||
*(.sbss2.*)
|
||||
*(.gnu.linkonce.sb2.*)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN (8);
|
||||
_bss_end = ABSOLUTE(.);
|
||||
} >iram1_0_seg :iram1_0_phdr
|
||||
|
||||
.lit4 : ALIGN(4)
|
||||
{
|
||||
_lit4_start = ABSOLUTE(.);
|
||||
*(*.lit4)
|
||||
*(.lit4.*)
|
||||
*(.gnu.linkonce.lit4.*)
|
||||
_lit4_end = ABSOLUTE(.);
|
||||
} >iram1_0_seg :iram1_0_phdr
|
||||
|
||||
.irom0.text : ALIGN(4)
|
||||
{
|
||||
_irom0_text_start = ABSOLUTE(.);
|
||||
*(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)
|
||||
_irom0_text_end = ABSOLUTE(.);
|
||||
} >irom0_0_seg :irom0_0_phdr
|
||||
}
|
||||
|
||||
/* get ROM code address */
|
||||
INCLUDE "rom.ld"
|
344
bootloaders/eboot/rom.ld
Executable file
344
bootloaders/eboot/rom.ld
Executable file
@ -0,0 +1,344 @@
|
||||
PROVIDE ( Cache_Read_Disable = 0x400047f0 );
|
||||
PROVIDE ( Cache_Read_Enable = 0x40004678 );
|
||||
PROVIDE ( FilePacketSendReqMsgProc = 0x400035a0 );
|
||||
PROVIDE ( FlashDwnLdParamCfgMsgProc = 0x4000368c );
|
||||
PROVIDE ( FlashDwnLdStartMsgProc = 0x40003538 );
|
||||
PROVIDE ( FlashDwnLdStopReqMsgProc = 0x40003658 );
|
||||
PROVIDE ( GetUartDevice = 0x40003f4c );
|
||||
PROVIDE ( MD5Final = 0x40009900 );
|
||||
PROVIDE ( MD5Init = 0x40009818 );
|
||||
PROVIDE ( MD5Update = 0x40009834 );
|
||||
PROVIDE ( MemDwnLdStartMsgProc = 0x400036c4 );
|
||||
PROVIDE ( MemDwnLdStopReqMsgProc = 0x4000377c );
|
||||
PROVIDE ( MemPacketSendReqMsgProc = 0x400036f0 );
|
||||
PROVIDE ( RcvMsg = 0x40003eac );
|
||||
PROVIDE ( SHA1Final = 0x4000b648 );
|
||||
PROVIDE ( SHA1Init = 0x4000b584 );
|
||||
PROVIDE ( SHA1Transform = 0x4000a364 );
|
||||
PROVIDE ( SHA1Update = 0x4000b5a8 );
|
||||
PROVIDE ( Wait_SPI_Idle = 0x4000448c );
|
||||
PROVIDE ( SPIEraseArea = 0x40004b44 );
|
||||
PROVIDE ( SPIEraseBlock = 0x400049b4 );
|
||||
PROVIDE ( SPIEraseChip = 0x40004984 );
|
||||
PROVIDE ( SPIEraseSector = 0x40004a00 );
|
||||
PROVIDE ( SPILock = 0x400048a8 );
|
||||
PROVIDE ( SPIParamCfg = 0x40004c2c );
|
||||
PROVIDE ( SPIRead = 0x40004b1c );
|
||||
PROVIDE ( SPIReadModeCnfig = 0x400048ec );
|
||||
PROVIDE ( SPIUnlock = 0x40004878 );
|
||||
PROVIDE ( SPIWrite = 0x40004a4c );
|
||||
PROVIDE ( SelectSpiFunction = 0x40003f58 );
|
||||
PROVIDE ( SendMsg = 0x40003cf4 );
|
||||
PROVIDE ( UartConnCheck = 0x40003230 );
|
||||
PROVIDE ( UartConnectProc = 0x400037a0 );
|
||||
PROVIDE ( UartDwnLdProc = 0x40003368 );
|
||||
PROVIDE ( UartGetCmdLn = 0x40003ef4 );
|
||||
PROVIDE ( UartRegReadProc = 0x4000381c );
|
||||
PROVIDE ( UartRegWriteProc = 0x400037ac );
|
||||
PROVIDE ( UartRxString = 0x40003c30 );
|
||||
PROVIDE ( Uart_Init = 0x40003a14 );
|
||||
PROVIDE ( _DebugExceptionVector = 0x40000010 );
|
||||
PROVIDE ( _DoubleExceptionVector = 0x40000070 );
|
||||
PROVIDE ( _KernelExceptionVector = 0x40000030 );
|
||||
PROVIDE ( _NMIExceptionVector = 0x40000020 );
|
||||
PROVIDE ( _ResetHandler = 0x400000a4 );
|
||||
PROVIDE ( _ResetVector = 0x40000080 );
|
||||
PROVIDE ( _UserExceptionVector = 0x40000050 );
|
||||
PROVIDE ( __adddf3 = 0x4000c538 );
|
||||
PROVIDE ( __addsf3 = 0x4000c180 );
|
||||
PROVIDE ( __divdf3 = 0x4000cb94 );
|
||||
PROVIDE ( __divdi3 = 0x4000ce60 );
|
||||
PROVIDE ( __divsi3 = 0x4000dc88 );
|
||||
PROVIDE ( __extendsfdf2 = 0x4000cdfc );
|
||||
PROVIDE ( __fixdfsi = 0x4000ccb8 );
|
||||
PROVIDE ( __fixunsdfsi = 0x4000cd00 );
|
||||
PROVIDE ( __fixunssfsi = 0x4000c4c4 );
|
||||
PROVIDE ( __floatsidf = 0x4000e2f0 );
|
||||
PROVIDE ( __floatsisf = 0x4000e2ac );
|
||||
PROVIDE ( __floatunsidf = 0x4000e2e8 );
|
||||
PROVIDE ( __floatunsisf = 0x4000e2a4 );
|
||||
PROVIDE ( __muldf3 = 0x4000c8f0 );
|
||||
PROVIDE ( __muldi3 = 0x40000650 );
|
||||
PROVIDE ( __mulsf3 = 0x4000c3dc );
|
||||
PROVIDE ( __subdf3 = 0x4000c688 );
|
||||
PROVIDE ( __subsf3 = 0x4000c268 );
|
||||
PROVIDE ( __truncdfsf2 = 0x4000cd5c );
|
||||
PROVIDE ( __udivdi3 = 0x4000d310 );
|
||||
PROVIDE ( __udivsi3 = 0x4000e21c );
|
||||
PROVIDE ( __umoddi3 = 0x4000d770 );
|
||||
PROVIDE ( __umodsi3 = 0x4000e268 );
|
||||
PROVIDE ( __umulsidi3 = 0x4000dcf0 );
|
||||
PROVIDE ( _rom_store = 0x4000e388 );
|
||||
PROVIDE ( _rom_store_table = 0x4000e328 );
|
||||
PROVIDE ( _start = 0x4000042c );
|
||||
PROVIDE ( _xtos_alloca_handler = 0x4000dbe0 );
|
||||
PROVIDE ( _xtos_c_wrapper_handler = 0x40000598 );
|
||||
PROVIDE ( _xtos_cause3_handler = 0x40000590 );
|
||||
PROVIDE ( _xtos_ints_off = 0x4000bda4 );
|
||||
PROVIDE ( _xtos_ints_on = 0x4000bd84 );
|
||||
PROVIDE ( _xtos_l1int_handler = 0x4000048c );
|
||||
PROVIDE ( _xtos_p_none = 0x4000dbf8 );
|
||||
PROVIDE ( _xtos_restore_intlevel = 0x4000056c );
|
||||
PROVIDE ( _xtos_return_from_exc = 0x4000dc54 );
|
||||
PROVIDE ( _xtos_set_exception_handler = 0x40000454 );
|
||||
PROVIDE ( _xtos_set_interrupt_handler = 0x4000bd70 );
|
||||
PROVIDE ( _xtos_set_interrupt_handler_arg = 0x4000bd28 );
|
||||
PROVIDE ( _xtos_set_intlevel = 0x4000dbfc );
|
||||
PROVIDE ( _xtos_set_min_intlevel = 0x4000dc18 );
|
||||
PROVIDE ( _xtos_set_vpri = 0x40000574 );
|
||||
PROVIDE ( _xtos_syscall_handler = 0x4000dbe4 );
|
||||
PROVIDE ( _xtos_unhandled_exception = 0x4000dc44 );
|
||||
PROVIDE ( _xtos_unhandled_interrupt = 0x4000dc3c );
|
||||
PROVIDE ( aes_decrypt = 0x400092d4 );
|
||||
PROVIDE ( aes_decrypt_deinit = 0x400092e4 );
|
||||
PROVIDE ( aes_decrypt_init = 0x40008ea4 );
|
||||
PROVIDE ( aes_unwrap = 0x40009410 );
|
||||
PROVIDE ( base64_decode = 0x40009648 );
|
||||
PROVIDE ( base64_encode = 0x400094fc );
|
||||
PROVIDE ( bzero = 0x4000de84 );
|
||||
PROVIDE ( cmd_parse = 0x40000814 );
|
||||
PROVIDE ( conv_str_decimal = 0x40000b24 );
|
||||
PROVIDE ( conv_str_hex = 0x40000cb8 );
|
||||
PROVIDE ( convert_para_str = 0x40000a60 );
|
||||
PROVIDE ( dtm_get_intr_mask = 0x400026d0 );
|
||||
PROVIDE ( dtm_params_init = 0x4000269c );
|
||||
PROVIDE ( dtm_set_intr_mask = 0x400026c8 );
|
||||
PROVIDE ( dtm_set_params = 0x400026dc );
|
||||
PROVIDE ( eprintf = 0x40001d14 );
|
||||
PROVIDE ( eprintf_init_buf = 0x40001cb8 );
|
||||
PROVIDE ( eprintf_to_host = 0x40001d48 );
|
||||
PROVIDE ( est_get_printf_buf_remain_len = 0x40002494 );
|
||||
PROVIDE ( est_reset_printf_buf_len = 0x4000249c );
|
||||
PROVIDE ( ets_bzero = 0x40002ae8 );
|
||||
PROVIDE ( ets_char2xdigit = 0x40002b74 );
|
||||
PROVIDE ( ets_delay_us = 0x40002ecc );
|
||||
PROVIDE ( ets_enter_sleep = 0x400027b8 );
|
||||
PROVIDE ( ets_external_printf = 0x40002578 );
|
||||
PROVIDE ( ets_get_cpu_frequency = 0x40002f0c );
|
||||
PROVIDE ( ets_getc = 0x40002bcc );
|
||||
PROVIDE ( ets_install_external_printf = 0x40002450 );
|
||||
PROVIDE ( ets_install_putc1 = 0x4000242c );
|
||||
PROVIDE ( ets_install_putc2 = 0x4000248c );
|
||||
PROVIDE ( ets_install_uart_printf = 0x40002438 );
|
||||
PROVIDE ( ets_intr_lock = 0x40000f74 );
|
||||
PROVIDE ( ets_intr_unlock = 0x40000f80 );
|
||||
PROVIDE ( ets_isr_attach = 0x40000f88 );
|
||||
PROVIDE ( ets_isr_mask = 0x40000f98 );
|
||||
PROVIDE ( ets_isr_unmask = 0x40000fa8 );
|
||||
PROVIDE ( ets_memcmp = 0x400018d4 );
|
||||
PROVIDE ( ets_memcpy = 0x400018b4 );
|
||||
PROVIDE ( ets_memmove = 0x400018c4 );
|
||||
PROVIDE ( ets_memset = 0x400018a4 );
|
||||
PROVIDE ( ets_post = 0x40000e24 );
|
||||
PROVIDE ( ets_printf = 0x400024cc );
|
||||
PROVIDE ( ets_putc = 0x40002be8 );
|
||||
PROVIDE ( ets_rtc_int_register = 0x40002a40 );
|
||||
PROVIDE ( ets_run = 0x40000e04 );
|
||||
PROVIDE ( ets_set_idle_cb = 0x40000dc0 );
|
||||
PROVIDE ( ets_set_user_start = 0x40000fbc );
|
||||
PROVIDE ( ets_str2macaddr = 0x40002af8 );
|
||||
PROVIDE ( ets_strcmp = 0x40002aa8 );
|
||||
PROVIDE ( ets_strcpy = 0x40002a88 );
|
||||
PROVIDE ( ets_strlen = 0x40002ac8 );
|
||||
PROVIDE ( ets_strncmp = 0x40002ab8 );
|
||||
PROVIDE ( ets_strncpy = 0x40002a98 );
|
||||
PROVIDE ( ets_strstr = 0x40002ad8 );
|
||||
PROVIDE ( ets_task = 0x40000dd0 );
|
||||
PROVIDE ( ets_timer_arm = 0x40002cc4 );
|
||||
PROVIDE ( ets_timer_disarm = 0x40002d40 );
|
||||
PROVIDE ( ets_timer_done = 0x40002d80 );
|
||||
PROVIDE ( ets_timer_handler_isr = 0x40002da8 );
|
||||
PROVIDE ( ets_timer_init = 0x40002e68 );
|
||||
PROVIDE ( ets_timer_setfn = 0x40002c48 );
|
||||
PROVIDE ( ets_uart_printf = 0x40002544 );
|
||||
PROVIDE ( ets_update_cpu_frequency = 0x40002f04 );
|
||||
PROVIDE ( ets_vprintf = 0x40001f00 );
|
||||
PROVIDE ( ets_wdt_disable = 0x400030f0 );
|
||||
PROVIDE ( ets_wdt_enable = 0x40002fa0 );
|
||||
PROVIDE ( ets_wdt_get_mode = 0x40002f34 );
|
||||
PROVIDE ( ets_wdt_init = 0x40003170 );
|
||||
PROVIDE ( ets_wdt_restore = 0x40003158 );
|
||||
PROVIDE ( ets_write_char = 0x40001da0 );
|
||||
PROVIDE ( get_first_seg = 0x4000091c );
|
||||
PROVIDE ( gpio_init = 0x40004c50 );
|
||||
PROVIDE ( gpio_input_get = 0x40004cf0 );
|
||||
PROVIDE ( gpio_intr_ack = 0x40004dcc );
|
||||
PROVIDE ( gpio_intr_handler_register = 0x40004e28 );
|
||||
PROVIDE ( gpio_intr_pending = 0x40004d88 );
|
||||
PROVIDE ( gpio_intr_test = 0x40004efc );
|
||||
PROVIDE ( gpio_output_set = 0x40004cd0 );
|
||||
PROVIDE ( gpio_pin_intr_state_set = 0x40004d90 );
|
||||
PROVIDE ( gpio_pin_wakeup_disable = 0x40004ed4 );
|
||||
PROVIDE ( gpio_pin_wakeup_enable = 0x40004e90 );
|
||||
PROVIDE ( gpio_register_get = 0x40004d5c );
|
||||
PROVIDE ( gpio_register_set = 0x40004d04 );
|
||||
PROVIDE ( hmac_md5 = 0x4000a2cc );
|
||||
PROVIDE ( hmac_md5_vector = 0x4000a160 );
|
||||
PROVIDE ( hmac_sha1 = 0x4000ba28 );
|
||||
PROVIDE ( hmac_sha1_vector = 0x4000b8b4 );
|
||||
PROVIDE ( lldesc_build_chain = 0x40004f40 );
|
||||
PROVIDE ( lldesc_num2link = 0x40005050 );
|
||||
PROVIDE ( lldesc_set_owner = 0x4000507c );
|
||||
PROVIDE ( main = 0x40000fec );
|
||||
PROVIDE ( md5_vector = 0x400097ac );
|
||||
PROVIDE ( mem_calloc = 0x40001c2c );
|
||||
PROVIDE ( mem_free = 0x400019e0 );
|
||||
PROVIDE ( mem_init = 0x40001998 );
|
||||
PROVIDE ( mem_malloc = 0x40001b40 );
|
||||
PROVIDE ( mem_realloc = 0x40001c6c );
|
||||
PROVIDE ( mem_trim = 0x40001a14 );
|
||||
PROVIDE ( mem_zalloc = 0x40001c58 );
|
||||
PROVIDE ( memcmp = 0x4000dea8 );
|
||||
PROVIDE ( memcpy = 0x4000df48 );
|
||||
PROVIDE ( memmove = 0x4000e04c );
|
||||
PROVIDE ( memset = 0x4000e190 );
|
||||
PROVIDE ( multofup = 0x400031c0 );
|
||||
PROVIDE ( pbkdf2_sha1 = 0x4000b840 );
|
||||
PROVIDE ( phy_get_romfuncs = 0x40006b08 );
|
||||
PROVIDE ( rand = 0x40000600 );
|
||||
PROVIDE ( rc4_skip = 0x4000dd68 );
|
||||
PROVIDE ( recv_packet = 0x40003d08 );
|
||||
PROVIDE ( remove_head_space = 0x40000a04 );
|
||||
PROVIDE ( rijndaelKeySetupDec = 0x40008dd0 );
|
||||
PROVIDE ( rijndaelKeySetupEnc = 0x40009300 );
|
||||
PROVIDE ( rom_abs_temp = 0x400060c0 );
|
||||
PROVIDE ( rom_ana_inf_gating_en = 0x40006b10 );
|
||||
PROVIDE ( rom_cal_tos_v50 = 0x40007a28 );
|
||||
PROVIDE ( rom_chip_50_set_channel = 0x40006f84 );
|
||||
PROVIDE ( rom_chip_v5_disable_cca = 0x400060d0 );
|
||||
PROVIDE ( rom_chip_v5_enable_cca = 0x400060ec );
|
||||
PROVIDE ( rom_chip_v5_rx_init = 0x4000711c );
|
||||
PROVIDE ( rom_chip_v5_sense_backoff = 0x4000610c );
|
||||
PROVIDE ( rom_chip_v5_tx_init = 0x4000718c );
|
||||
PROVIDE ( rom_dc_iq_est = 0x4000615c );
|
||||
PROVIDE ( rom_en_pwdet = 0x400061b8 );
|
||||
PROVIDE ( rom_get_bb_atten = 0x40006238 );
|
||||
PROVIDE ( rom_get_corr_power = 0x40006260 );
|
||||
PROVIDE ( rom_get_fm_sar_dout = 0x400062dc );
|
||||
PROVIDE ( rom_get_noisefloor = 0x40006394 );
|
||||
PROVIDE ( rom_get_power_db = 0x400063b0 );
|
||||
PROVIDE ( rom_i2c_readReg = 0x40007268 );
|
||||
PROVIDE ( rom_i2c_readReg_Mask = 0x4000729c );
|
||||
PROVIDE ( rom_i2c_writeReg = 0x400072d8 );
|
||||
PROVIDE ( rom_i2c_writeReg_Mask = 0x4000730c );
|
||||
PROVIDE ( rom_iq_est_disable = 0x40006400 );
|
||||
PROVIDE ( rom_iq_est_enable = 0x40006430 );
|
||||
PROVIDE ( rom_linear_to_db = 0x40006484 );
|
||||
PROVIDE ( rom_mhz2ieee = 0x400065a4 );
|
||||
PROVIDE ( rom_pbus_dco___SA2 = 0x40007bf0 );
|
||||
PROVIDE ( rom_pbus_debugmode = 0x4000737c );
|
||||
PROVIDE ( rom_pbus_enter_debugmode = 0x40007410 );
|
||||
PROVIDE ( rom_pbus_exit_debugmode = 0x40007448 );
|
||||
PROVIDE ( rom_pbus_force_test = 0x4000747c );
|
||||
PROVIDE ( rom_pbus_rd = 0x400074d8 );
|
||||
PROVIDE ( rom_pbus_set_rxgain = 0x4000754c );
|
||||
PROVIDE ( rom_pbus_set_txgain = 0x40007610 );
|
||||
PROVIDE ( rom_pbus_workmode = 0x40007648 );
|
||||
PROVIDE ( rom_pbus_xpd_rx_off = 0x40007688 );
|
||||
PROVIDE ( rom_pbus_xpd_rx_on = 0x400076cc );
|
||||
PROVIDE ( rom_pbus_xpd_tx_off = 0x400076fc );
|
||||
PROVIDE ( rom_pbus_xpd_tx_on = 0x40007740 );
|
||||
PROVIDE ( rom_pbus_xpd_tx_on__low_gain = 0x400077a0 );
|
||||
PROVIDE ( rom_phy_reset_req = 0x40007804 );
|
||||
PROVIDE ( rom_restart_cal = 0x4000781c );
|
||||
PROVIDE ( rom_rfcal_pwrctrl = 0x40007eb4 );
|
||||
PROVIDE ( rom_rfcal_rxiq = 0x4000804c );
|
||||
PROVIDE ( rom_rfcal_rxiq_set_reg = 0x40008264 );
|
||||
PROVIDE ( rom_rfcal_txcap = 0x40008388 );
|
||||
PROVIDE ( rom_rfcal_txiq = 0x40008610 );
|
||||
PROVIDE ( rom_rfcal_txiq_cover = 0x400088b8 );
|
||||
PROVIDE ( rom_rfcal_txiq_set_reg = 0x40008a70 );
|
||||
PROVIDE ( rom_rfpll_reset = 0x40007868 );
|
||||
PROVIDE ( rom_rfpll_set_freq = 0x40007968 );
|
||||
PROVIDE ( rom_rxiq_cover_mg_mp = 0x40008b6c );
|
||||
PROVIDE ( rom_rxiq_get_mis = 0x40006628 );
|
||||
PROVIDE ( rom_sar_init = 0x40006738 );
|
||||
PROVIDE ( rom_set_ana_inf_tx_scale = 0x4000678c );
|
||||
PROVIDE ( rom_set_channel_freq = 0x40006c50 );
|
||||
PROVIDE ( rom_set_loopback_gain = 0x400067c8 );
|
||||
PROVIDE ( rom_set_noise_floor = 0x40006830 );
|
||||
PROVIDE ( rom_set_rxclk_en = 0x40006550 );
|
||||
PROVIDE ( rom_set_txbb_atten = 0x40008c6c );
|
||||
PROVIDE ( rom_set_txclk_en = 0x4000650c );
|
||||
PROVIDE ( rom_set_txiq_cal = 0x40008d34 );
|
||||
PROVIDE ( rom_start_noisefloor = 0x40006874 );
|
||||
PROVIDE ( rom_start_tx_tone = 0x400068b4 );
|
||||
PROVIDE ( rom_stop_tx_tone = 0x4000698c );
|
||||
PROVIDE ( rom_tx_mac_disable = 0x40006a98 );
|
||||
PROVIDE ( rom_tx_mac_enable = 0x40006ad4 );
|
||||
PROVIDE ( rom_txtone_linear_pwr = 0x40006a1c );
|
||||
PROVIDE ( rom_write_rfpll_sdm = 0x400078dc );
|
||||
PROVIDE ( roundup2 = 0x400031b4 );
|
||||
PROVIDE ( rtc_enter_sleep = 0x40002870 );
|
||||
PROVIDE ( rtc_get_reset_reason = 0x400025e0 );
|
||||
PROVIDE ( rtc_intr_handler = 0x400029ec );
|
||||
PROVIDE ( rtc_set_sleep_mode = 0x40002668 );
|
||||
PROVIDE ( save_rxbcn_mactime = 0x400027a4 );
|
||||
PROVIDE ( save_tsf_us = 0x400027ac );
|
||||
PROVIDE ( send_packet = 0x40003c80 );
|
||||
PROVIDE ( sha1_prf = 0x4000ba48 );
|
||||
PROVIDE ( sha1_vector = 0x4000a2ec );
|
||||
PROVIDE ( sip_alloc_to_host_evt = 0x40005180 );
|
||||
PROVIDE ( sip_get_ptr = 0x400058a8 );
|
||||
PROVIDE ( sip_get_state = 0x40005668 );
|
||||
PROVIDE ( sip_init_attach = 0x4000567c );
|
||||
PROVIDE ( sip_install_rx_ctrl_cb = 0x4000544c );
|
||||
PROVIDE ( sip_install_rx_data_cb = 0x4000545c );
|
||||
PROVIDE ( sip_post = 0x400050fc );
|
||||
PROVIDE ( sip_post_init = 0x400056c4 );
|
||||
PROVIDE ( sip_reclaim_from_host_cmd = 0x4000534c );
|
||||
PROVIDE ( sip_reclaim_tx_data_pkt = 0x400052c0 );
|
||||
PROVIDE ( sip_send = 0x40005808 );
|
||||
PROVIDE ( sip_to_host_chain_append = 0x40005864 );
|
||||
PROVIDE ( sip_to_host_evt_send_done = 0x40005234 );
|
||||
PROVIDE ( slc_add_credits = 0x400060ac );
|
||||
PROVIDE ( slc_enable = 0x40005d90 );
|
||||
PROVIDE ( slc_from_host_chain_fetch = 0x40005f24 );
|
||||
PROVIDE ( slc_from_host_chain_recycle = 0x40005e94 );
|
||||
PROVIDE ( slc_init_attach = 0x40005c50 );
|
||||
PROVIDE ( slc_init_credit = 0x4000608c );
|
||||
PROVIDE ( slc_pause_from_host = 0x40006014 );
|
||||
PROVIDE ( slc_reattach = 0x40005c1c );
|
||||
PROVIDE ( slc_resume_from_host = 0x4000603c );
|
||||
PROVIDE ( slc_select_tohost_gpio = 0x40005dc0 );
|
||||
PROVIDE ( slc_select_tohost_gpio_mode = 0x40005db8 );
|
||||
PROVIDE ( slc_send_to_host_chain = 0x40005de4 );
|
||||
PROVIDE ( slc_set_host_io_max_window = 0x40006068 );
|
||||
PROVIDE ( slc_to_host_chain_recycle = 0x40005f10 );
|
||||
PROVIDE ( software_reset = 0x4000264c );
|
||||
PROVIDE ( spi_flash_attach = 0x40004644 );
|
||||
PROVIDE ( srand = 0x400005f0 );
|
||||
PROVIDE ( strcmp = 0x4000bdc8 );
|
||||
PROVIDE ( strcpy = 0x4000bec8 );
|
||||
PROVIDE ( strlen = 0x4000bf4c );
|
||||
PROVIDE ( strncmp = 0x4000bfa8 );
|
||||
PROVIDE ( strncpy = 0x4000c0a0 );
|
||||
PROVIDE ( strstr = 0x4000e1e0 );
|
||||
PROVIDE ( timer_insert = 0x40002c64 );
|
||||
PROVIDE ( uartAttach = 0x4000383c );
|
||||
PROVIDE ( uart_baudrate_detect = 0x40003924 );
|
||||
PROVIDE ( uart_buff_switch = 0x400038a4 );
|
||||
PROVIDE ( uart_div_modify = 0x400039d8 );
|
||||
PROVIDE ( uart_rx_intr_handler = 0x40003bbc );
|
||||
PROVIDE ( uart_rx_one_char = 0x40003b8c );
|
||||
PROVIDE ( uart_rx_one_char_block = 0x40003b64 );
|
||||
PROVIDE ( uart_rx_readbuff = 0x40003ec8 );
|
||||
PROVIDE ( uart_tx_one_char = 0x40003b30 );
|
||||
PROVIDE ( wepkey_128 = 0x4000bc40 );
|
||||
PROVIDE ( wepkey_64 = 0x4000bb3c );
|
||||
PROVIDE ( xthal_bcopy = 0x40000688 );
|
||||
PROVIDE ( xthal_copy123 = 0x4000074c );
|
||||
PROVIDE ( xthal_get_ccompare = 0x4000dd4c );
|
||||
PROVIDE ( xthal_get_ccount = 0x4000dd38 );
|
||||
PROVIDE ( xthal_get_interrupt = 0x4000dd58 );
|
||||
PROVIDE ( xthal_get_intread = 0x4000dd58 );
|
||||
PROVIDE ( xthal_memcpy = 0x400006c4 );
|
||||
PROVIDE ( xthal_set_ccompare = 0x4000dd40 );
|
||||
PROVIDE ( xthal_set_intclear = 0x4000dd60 );
|
||||
PROVIDE ( xthal_spill_registers_into_stack_nw = 0x4000e320 );
|
||||
PROVIDE ( xthal_window_spill = 0x4000e324 );
|
||||
PROVIDE ( xthal_window_spill_nw = 0x4000e320 );
|
||||
|
||||
PROVIDE ( Te0 = 0x3fffccf0 );
|
||||
PROVIDE ( UartDev = 0x3fffde10 );
|
||||
PROVIDE ( flashchip = 0x3fffc714);
|
Loading…
x
Reference in New Issue
Block a user