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Initial ESP8266 HW SPI implementation

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ILI9341 lib as a client for SPI lib
This commit is contained in:
Andrey Filimonov
2015-04-01 07:10:31 +03:00
parent 61f3d12909
commit 4626a9df80
24 changed files with 2227 additions and 76 deletions
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95
libraries/SPI/HSPI.cpp Normal file
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@ -0,0 +1,95 @@
#include "include\HSPI.h"
#include "include\spi_register.h"
#define __min(a,b) ((a > b) ? (b):(a))
void HSPI::begin()
{
spi_fifo = (uint32_t*)SPI_FLASH_C0(hspi_port);
//bit9 of PERIPHS_IO_MUX should be cleared when HSPI clock doesn't equal CPU clock
WRITE_PERI_REG(PERIPHS_IO_MUX, 0x105);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDI_U, FUNC_HSPIQ_MISO); // gpio12
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, FUNC_HSPID_MOSI); // gpio13
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTMS_U, FUNC_HSPI_CLK); // gpio14
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, FUNC_HSPI_CS0); // gpio15
uint32_t regvalue = SPI_FLASH_DOUT;
regvalue |= SPI_DOUTDIN | SPI_CK_I_EDGE;
regvalue &= ~(BIT2 | SPI_FLASH_USR_ADDR | SPI_FLASH_USR_DUMMY | SPI_FLASH_USR_DIN | SPI_USR_COMMAND);
SET_PERI_REG_MASK(SPI_FLASH_USER(hspi_port), regvalue);
// SPI clock=CPU clock/8
WRITE_PERI_REG(SPI_FLASH_CLOCK(hspi_port),
((1&SPI_CLKDIV_PRE)<<SPI_CLKDIV_PRE_S)|
((3&SPI_CLKCNT_N)<<SPI_CLKCNT_N_S)|
((1&SPI_CLKCNT_H)<<SPI_CLKCNT_H_S)|
((3&SPI_CLKCNT_L)<<SPI_CLKCNT_L_S)); //clear bit 31,set SPI clock div
}
void HSPI::end()
{
}
void HSPI::setDataMode(uint8_t dataMode)
{
}
void HSPI::setBitOrder(uint8_t bitOrder)
{
if (!bitOrder)
{
WRITE_PERI_REG(SPI_FLASH_CTRL(hspi_port),
READ_PERI_REG(SPI_FLASH_CTRL(hspi_port)) & (~(SPI_WR_BIT_ODER | SPI_RD_BIT_ODER)));
}
else
{
WRITE_PERI_REG(SPI_FLASH_CTRL(hspi_port),
READ_PERI_REG(SPI_FLASH_CTRL(hspi_port)) | (SPI_WR_BIT_ODER | SPI_RD_BIT_ODER));
}
}
void HSPI::setClockDivider(uint8_t clockDiv)
{
uint32_t clock_reg_val = (((clockDiv - 1) & SPI_CLKDIV_PRE) << SPI_CLKDIV_PRE_S) |
((1 & SPI_CLKCNT_N) << SPI_CLKCNT_N_S) |
((0 & SPI_CLKCNT_H) << SPI_CLKCNT_H_S) |
((1 & SPI_CLKCNT_L) << SPI_CLKCNT_L_S);
WRITE_PERI_REG(SPI_FLASH_CLOCK(hspi_port), clock_reg_val);
}
uint8_t HSPI::transfer(uint8_t data)
{
hspi_wait_ready();
hspi_prepare_txrx(1);
*spi_fifo = data;
hspi_start_tx();
hspi_wait_ready();
return *spi_fifo & 0xFF;
}
uint16_t HSPI::transfer16(uint16_t data)
{
hspi_wait_ready();
hspi_prepare_txrx(2);
*spi_fifo = data;
hspi_start_tx();
hspi_wait_ready();
return *spi_fifo & 0xFFFF;
}
void HSPI::transfer(void *buf, size_t count)
{
uint32_t *_data = (uint32_t*)buf;
uint8_t i;
uint8_t words_to_send = __min((count + 3) / 4, hspi_fifo_size);
hspi_prepare_tx(count);
for(i = 0; i < words_to_send;i++)
spi_fifo[i] = _data[i];
hspi_start_tx();
}

20
libraries/SPI/SPI.cpp
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@ -11,7 +11,7 @@
*/
#include "SPI.h"
#include "HSPI.h"
#include "include\HSPI.h"
SPIClass SPI;
@ -38,13 +38,29 @@ void SPIClass::end()
_impl = 0;
}
void SPIClass::beginTransaction(SPISettings settings)
{
if (!_impl)
return;
_impl->setBitOrder(settings._bitOrder);
_impl->setDataMode(settings._dataMode);
_impl->setClockDivider(settings._clock);
}
uint8_t SPIClass::transfer(uint8_t data)
{
if (!_impl)
return;
return 0;
return _impl->transfer(data);
}
uint16_t SPIClass::transfer16(uint16_t data)
{
if (!_impl)
return 0;
return _impl->transfer16(data);
}
void SPIClass::transfer(void *buf, size_t count)
{
if (!_impl)

7
libraries/SPI/SPI.h
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@ -14,6 +14,7 @@
#define _SPI_H_INCLUDED
#include <Arduino.h>
#include <stdlib.h>
#include "include/SPIdef.h"
@ -42,11 +43,11 @@ public:
void begin();
// void usingInterrupt(uint8_t interruptNumber);
// void beginTransaction(SPISettings settings);
void beginTransaction(SPISettings settings);
uint8_t transfer(uint8_t data);
// uint16_t transfer16(uint16_t data);
uint16_t transfer16(uint16_t data);
void transfer(void *buf, size_t count);
// void endTransaction(void);
void endTransaction(void);
void end();

93
libraries/SPI/include/HSPI.h
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@ -14,78 +14,35 @@ extern "C" {
class HSPI : public SPIImpl
{
public:
virtual void begin()
{
//bit9 of PERIPHS_IO_MUX should be cleared when HSPI clock doesn't equal CPU clock
WRITE_PERI_REG(PERIPHS_IO_MUX, 0x105);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDI_U, FUNC_HSPIQ_MISO); // gpio12
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, FUNC_HSPID_MOSI); // gpio13
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTMS_U, FUNC_HSPI_CLK); // gpio14
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, FUNC_HSPI_CS0); // gpio15
SET_PERI_REG_MASK(SPI_USER(HSPI), SPI_CS_SETUP|SPI_CS_HOLD|SPI_USR_COMMAND);
CLEAR_PERI_REG_MASK(SPI_USER(HSPI), SPI_FLASH_MODE);
// SPI clock=CPU clock/8
WRITE_PERI_REG(SPI_CLOCK(HSPI),
((1&SPI_CLKDIV_PRE)<<SPI_CLKDIV_PRE_S)|
((3&SPI_CLKCNT_N)<<SPI_CLKCNT_N_S)|
((1&SPI_CLKCNT_H)<<SPI_CLKCNT_H_S)|
((3&SPI_CLKCNT_L)<<SPI_CLKCNT_L_S)); //clear bit 31,set SPI clock div
SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_CS_SETUP|SPI_CS_HOLD|SPI_USR_COMMAND|SPI_USR_MOSI);
CLEAR_PERI_REG_MASK(SPI_USER(spi_no), SPI_FLASH_MODE);
//clear Daul or Quad lines transmission mode
CLEAR_PERI_REG_MASK(SPI_CTRL(spi_no), SPI_QIO_MODE|SPI_DIO_MODE|SPI_DOUT_MODE|SPI_QOUT_MODE);
WRITE_PERI_REG(SPI_CLOCK(spi_no),
((3&SPI_CLKCNT_N)<<SPI_CLKCNT_N_S)|
((1&SPI_CLKCNT_H)<<SPI_CLKCNT_H_S)|
((3&SPI_CLKCNT_L)<<SPI_CLKCNT_L_S)); //clear bit 31,set SPI clock div
//set 8bit output buffer length, the buffer is the low 8bit of register"SPI_FLASH_C0"
WRITE_PERI_REG(SPI_USER1(spi_no),
((7&SPI_USR_MOSI_BITLEN)<<SPI_USR_MOSI_BITLEN_S)|
((7&SPI_USR_MISO_BITLEN)<<SPI_USR_MISO_BITLEN_S));
}
virtual void end()
{
}
virtual void setBitOrder(uint8_t bitOrder)
{
}
virtual void setDataMode(uint8_t dataMode)
{
}
virtual void setClockDivider(uint8_t clockDiv)
{
}
virtual uint8_t transfer(uint8_t data)
{
}
virtual void transfer(void *buf, size_t count)
{
}
virtual void begin();
virtual void end();
virtual void setBitOrder(uint8_t bitOrder);
virtual void setDataMode(uint8_t dataMode);
virtual void setClockDivider(uint8_t clockDiv);
virtual uint8_t transfer(uint8_t data);
virtual uint16_t transfer16(uint16_t data);
virtual void transfer(void *buf, size_t count);
private:
uint32_t _clkDiv;
uint32_t *spi_fifo;
const uint32_t hspi_port = 1;
const uint32_t hspi_fifo_size = 32;
private:
inline void hspi_wait_ready(void){while (READ_PERI_REG(SPI_FLASH_CMD(hspi_port))&SPI_FLASH_USR);}
inline void hspi_start_tx(){SET_PERI_REG_MASK(SPI_FLASH_CMD(hspi_port), SPI_FLASH_USR);}
inline void hspi_prepare_tx(uint32_t bytecount)
{
uint32_t bitcount = bytecount * 8 - 1;
WRITE_PERI_REG(SPI_FLASH_USER1(hspi_port), (bitcount & SPI_USR_OUT_BITLEN) << SPI_USR_OUT_BITLEN_S);
}
inline void hspi_prepare_txrx(uint32_t bytecount)
{
uint32_t bitcount = bytecount * 8 - 1;
WRITE_PERI_REG(SPI_FLASH_USER1(hspi_port), ((bitcount & SPI_USR_OUT_BITLEN) << SPI_USR_OUT_BITLEN_S) |
((bitcount & SPI_USR_DIN_BITLEN) << SPI_USR_DIN_BITLEN_S));
}
};

6
libraries/SPI/include/SPIImpl.h
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@ -1,20 +1,20 @@
#ifndef SPIIMPL_H
#define SPIIMPL_H
#include <stdint.h>
#include <cstdlib>
#include <Arduino.h>
class SPIImpl
{
public:
virtual void begin() = 0;
virtual uint8_t transfer(uint8_t data) = 0;
virtual uint16_t transfer16(uint16_t data) = 0;
virtual void transfer(void *buf, size_t count) = 0;
virtual void end() = 0;
virtual void setBitOrder(uint8_t bitOrder) = 0;
virtual void setDataMode(uint8_t dataMode) = 0;
virtual void setClockDivider(uint8_t clockDiv) = 0;
};

239
libraries/SPI/include/spi_register.h Normal file
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@ -0,0 +1,239 @@
//Generated at 2014-07-29 11:03:29
/*
* Copyright (c) 2010 - 2011 Espressif System
*
*/
#ifndef SPI_REGISTER_H_INCLUDED
#define SPI_REGISTER_H_INCLUDED
#define REG_SPI_BASE(i) (0x60000200-i*0x100)
#define SPI_FLASH_CMD(i) (REG_SPI_BASE(i) + 0x0)
#define SPI_FLASH_READ (BIT(31))
#define SPI_FLASH_WREN (BIT(30))
#define SPI_FLASH_WRDI (BIT(29))
#define SPI_FLASH_RDID (BIT(28))
#define SPI_FLASH_RDSR (BIT(27))
#define SPI_FLASH_WRSR (BIT(26))
#define SPI_FLASH_PP (BIT(25))
#define SPI_FLASH_SE (BIT(24))
#define SPI_FLASH_BE (BIT(23))
#define SPI_FLASH_CE (BIT(22))
#define SPI_FLASH_DP (BIT(21))
#define SPI_FLASH_RES (BIT(20))
#define SPI_FLASH_HPM (BIT(19))
#define SPI_FLASH_USR (BIT(18))
#define SPI_FLASH_ADDR(i) (REG_SPI_BASE(i) + 0x4)
#define SPI_FLASH_CTRL(i) (REG_SPI_BASE(i) + 0x8)
#define SPI_WR_BIT_ODER (BIT(26))
#define SPI_RD_BIT_ODER (BIT(25))
#define SPI_QIO_MODE (BIT(24))
#define SPI_DIO_MODE (BIT(23))
#define SPI_TWO_BYTE_STATUS_EN (BIT(22))
#define SPI_WP_REG (BIT(21))
#define SPI_QOUT_MODE (BIT(20))
#define SPI_SHARE_BUS (BIT(19))
#define SPI_HOLD_MODE (BIT(18))
#define SPI_ENABLE_AHB (BIT(17))
#define SPI_SST_AAI (BIT(16))
#define SPI_RESANDRES (BIT(15))
#define SPI_DOUT_MODE (BIT(14))
#define SPI_FASTRD_MODE (BIT(13))
#define SPI_FLASH_CTRL1(i) (REG_SPI_BASE (i) + 0xC)
#define SPI_T_CSH 0x0000000F
#define SPI_T_CSH_S 28
#define SPI_T_RES 0x00000FFF
#define SPI_T_RES_S 16
#define SPI_BUS_TIMER_LIMIT 0x0000FFFF
#define SPI_BUS_TIMER_LIMIT_S 0
#define SPI_FLASH_STATUS(i) (REG_SPI_BASE(i) + 0x10)
#define SPI_STATUS_EXT 0x000000FF
#define SPI_STATUS_EXT_S 24
#define SPI_WB_MODE 0x000000FF
#define SPI_WB_MODE_S 16
#define SPI_FLASH_STATUS_PRO_FLAG (BIT(7))
#define SPI_FLASH_TOP_BOT_PRO_FLAG (BIT(5))
#define SPI_FLASH_BP2 (BIT(4))
#define SPI_FLASH_BP1 (BIT(3))
#define SPI_FLASH_BP0 (BIT(2))
#define SPI_FLASH_WRENABLE_FLAG (BIT(1))
#define SPI_FLASH_BUSY_FLAG (BIT(0))
#define SPI_FLASH_CTRL2(i) (REG_SPI_BASE(i) + 0x14)
#define SPI_CS_DELAY_NUM 0x0000000F
#define SPI_CS_DELAY_NUM_S 28
#define SPI_CS_DELAY_MODE 0x00000003
#define SPI_CS_DELAY_MODE_S 26
#define SPI_MOSI_DELAY_NUM 0x00000007
#define SPI_MOSI_DELAY_NUM_S 23
#define SPI_MOSI_DELAY_MODE 0x00000003
#define SPI_MOSI_DELAY_MODE_S 21
#define SPI_MISO_DELAY_NUM 0x00000007
#define SPI_MISO_DELAY_NUM_S 18
#define SPI_MISO_DELAY_MODE 0x00000003
#define SPI_MISO_DELAY_MODE_S 16
#define SPI_CK_OUT_HIGH_MODE 0x0000000F
#define SPI_CK_OUT_HIGH_MODE_S 12
#define SPI_CK_OUT_LOW_MODE 0x0000000F
#define SPI_CK_OUT_LOW_MODE_S 8
#define SPI_HOLD_TIME 0x0000000F
#define SPI_HOLD_TIME_S 4
#define SPI_SETUP_TIME 0x0000000F
#define SPI_SETUP_TIME_S 0
#define SPI_FLASH_CLOCK(i) (REG_SPI_BASE(i) + 0x18)
#define SPI_CLK_EQU_SYSCLK (BIT(31))
#define SPI_CLKDIV_PRE 0x00001FFF
#define SPI_CLKDIV_PRE_S 18
#define SPI_CLKCNT_N 0x0000003F
#define SPI_CLKCNT_N_S 12
#define SPI_CLKCNT_H 0x0000003F
#define SPI_CLKCNT_H_S 6
#define SPI_CLKCNT_L 0x0000003F
#define SPI_CLKCNT_L_S 0
#define SPI_FLASH_USER(i) (REG_SPI_BASE(i) + 0x1C)
#define SPI_USR_COMMAND (BIT(31))
#define SPI_FLASH_USR_ADDR (BIT(30))
#define SPI_FLASH_USR_DUMMY (BIT(29))
#define SPI_FLASH_USR_DIN (BIT(28))
#define SPI_FLASH_DOUT (BIT(27))
#define SPI_USR_DUMMY_IDLE (BIT(26))
#define SPI_USR_DOUT_HIGHPART (BIT(25))
#define SPI_USR_DIN_HIGHPART (BIT(24))
#define SPI_USR_PREP_HOLD (BIT(23))
#define SPI_USR_CMD_HOLD (BIT(22))
#define SPI_USR_ADDR_HOLD (BIT(21))
#define SPI_USR_DUMMY_HOLD (BIT(20))
#define SPI_USR_DIN_HOLD (BIT(19))
#define SPI_USR_DOUT_HOLD (BIT(18))
#define SPI_USR_HOLD_POL (BIT(17))
#define SPI_SIO (BIT(16))
#define SPI_FWRITE_QIO (BIT(15))
#define SPI_FWRITE_DIO (BIT(14))
#define SPI_FWRITE_QUAD (BIT(13))
#define SPI_FWRITE_DUAL (BIT(12))
#define SPI_WR_BYTE_ORDER (BIT(11))
#define SPI_RD_BYTE_ORDER (BIT(10))
#define SPI_AHB_ENDIAN_MODE 0x00000003
#define SPI_AHB_ENDIAN_MODE_S 8
#define SPI_CK_OUT_EDGE (BIT(7))
#define SPI_CK_I_EDGE (BIT(6))
#define SPI_CS_SETUP (BIT(5))
#define SPI_CS_HOLD (BIT(4))
#define SPI_AHB_USR_COMMAND (BIT(3))
#define SPI_AHB_USR_COMMAND_4BYTE (BIT(1))
#define SPI_DOUTDIN (BIT(0))
#define SPI_FLASH_USER1(i) (REG_SPI_BASE(i) + 0x20)
#define SPI_USR_ADDR_BITLEN 0x0000003F
#define SPI_USR_ADDR_BITLEN_S 26
#define SPI_USR_OUT_BITLEN 0x000001FF
#define SPI_USR_OUT_BITLEN_S 17
#define SPI_USR_DIN_BITLEN 0x000001FF
#define SPI_USR_DIN_BITLEN_S 8
#define SPI_USR_DUMMY_CYCLELEN 0x000000FF
#define SPI_USR_DUMMY_CYCLELEN_S 0
#define SPI_FLASH_USER2(i) (REG_SPI_BASE(i) + 0x24)
#define SPI_USR_COMMAND_BITLEN 0x0000000F
#define SPI_USR_COMMAND_BITLEN_S 28
#define SPI_USR_COMMAND_VALUE 0x0000FFFF
#define SPI_USR_COMMAND_VALUE_S 0
#define SPI_FLASH_USER3(i) (REG_SPI_BASE(i) + 0x28)
#define SPI_FLASH_PIN(i) (REG_SPI_BASE(i) + 0x2C)
#define SPI_FLASH_SLAVE(i) (REG_SPI_BASE(i) + 0x30)
#define SPI_SYNC_RESET (BIT(31))
#define SPI_SLAVE_MODE (BIT(30))
#define SPI_SLV_WR_RD_BUF_EN (BIT(29))
#define SPI_SLV_WR_RD_STA_EN (BIT(28))
#define SPI_SLV_CMD_DEFINE (BIT(27))
#define SPI_TRANS_CNT 0x0000000F
#define SPI_TRANS_CNT_S 23
#define SPI_SLV_LAST_STATE 0x00000007
#define SPI_SLV_LAST_STATE_S 20
#define SPI_SLV_LAST_COMMAND 0x00000007
#define SPI_SLV_LAST_COMMAND_S 17
#define SPI_CS_I_MODE 0x00000003
#define SPI_CS_I_MODE_S 10
#define SPI_INT_EN 0x0000001F
#define SPI_INT_EN_S 5
#define SPI_TRANS_DONE (BIT(4))
#define SPI_SLV_WR_STA_DONE (BIT(3))
#define SPI_SLV_RD_STA_DONE (BIT(2))
#define SPI_SLV_WR_BUF_DONE (BIT(1))
#define SPI_SLV_RD_BUF_DONE (BIT(0))
#define SPI_FLASH_SLAVE1(i) (REG_SPI_BASE(i) + 0x34)
#define SPI_SLV_STATUS_BITLEN 0x0000001F
#define SPI_SLV_STATUS_BITLEN_S 27
#define SPI_SLV_STATUS_FAST_EN (BIT(26))
#define SPI_SLV_STATUS_READBACK (BIT(25))
#define SPI_SLV_BUF_BITLEN 0x000001FF
#define SPI_SLV_BUF_BITLEN_S 16
#define SPI_SLV_RD_ADDR_BITLEN 0x0000003F
#define SPI_SLV_RD_ADDR_BITLEN_S 10
#define SPI_SLV_WR_ADDR_BITLEN 0x0000003F
#define SPI_SLV_WR_ADDR_BITLEN_S 4
#define SPI_SLV_WRSTA_DUMMY_EN (BIT(3))
#define SPI_SLV_RDSTA_DUMMY_EN (BIT(2))
#define SPI_SLV_WRBUF_DUMMY_EN (BIT(1))
#define SPI_SLV_RDBUF_DUMMY_EN (BIT(0))
#define SPI_FLASH_SLAVE2(i) (REG_SPI_BASE(i) + 0x38)
#define SPI_SLV_WRBUF_DUMMY_CYCLELEN 0x000000FF
#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_S 24
#define SPI_SLV_RDBUF_DUMMY_CYCLELEN 0x000000FF
#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_S 16
#define SPI_SLV_WRSTA_DUMMY_CYCLELEN 0x000000FF
#define SPI_SLV_WRSTA_DUMMY_CYCLELEN_S 8
#define SPI_SLV_RDSTA_DUMMY_CYCLELEN 0x000000FF
#define SPI_SLV_RDSTA_DUMMY_CYCLELEN_S 0
#define SPI_FLASH_SLAVE3(i) (REG_SPI_BASE(i) + 0x3C)
#define SPI_SLV_WRSTA_CMD_VALUE 0x000000FF
#define SPI_SLV_WRSTA_CMD_VALUE_S 24
#define SPI_SLV_RDSTA_CMD_VALUE 0x000000FF
#define SPI_SLV_RDSTA_CMD_VALUE_S 16
#define SPI_SLV_WRBUF_CMD_VALUE 0x000000FF
#define SPI_SLV_WRBUF_CMD_VALUE_S 8
#define SPI_SLV_RDBUF_CMD_VALUE 0x000000FF
#define SPI_SLV_RDBUF_CMD_VALUE_S 0
#define SPI_FLASH_C0(i) (REG_SPI_BASE(i) +0x40)
#define SPI_FLASH_C1(i) (REG_SPI_BASE(i) +0x44)
#define SPI_FLASH_C2(i) (REG_SPI_BASE(i) +0x48)
#define SPI_FLASH_C3(i) (REG_SPI_BASE(i) +0x4C)
#define SPI_FLASH_C4(i) (REG_SPI_BASE(i) +0x50)
#define SPI_FLASH_C5(i) (REG_SPI_BASE(i) +0x54)
#define SPI_FLASH_C6(i) (REG_SPI_BASE(i) +0x58)
#define SPI_FLASH_C7(i) (REG_SPI_BASE(i) +0x5C)
#define SPI_FLASH_EXT0(i) (REG_SPI_BASE(i) + 0xF0)
#define SPI_T_PP_ENA (BIT(31))
#define SPI_T_PP_SHIFT 0x0000000F
#define SPI_T_PP_SHIFT_S 16
#define SPI_T_PP_TIME 0x00000FFF
#define SPI_T_PP_TIME_S 0
#define SPI_FLASH_EXT1(i) (REG_SPI_BASE(i) + 0xF4)
#define SPI_T_ERASE_ENA (BIT(31))
#define SPI_T_ERASE_SHIFT 0x0000000F
#define SPI_T_ERASE_SHIFT_S 16
#define SPI_T_ERASE_TIME 0x00000FFF
#define SPI_T_ERASE_TIME_S 0
#define SPI_FLASH_EXT2(i) (REG_SPI_BASE(i) + 0xF8)
#define SPI_ST 0x00000007
#define SPI_ST_S 0
#define SPI_FLASH_EXT3(i) (REG_SPI_BASE(i) + 0xFC)
#define SPI_INT_HOLD_ENA 0x00000003
#define SPI_INT_HOLD_ENA_S 0
#endif // SPI_REGISTER_H_INCLUDED