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fix SPI speed calculation @160Mhz Clock

This commit is contained in:
Markus Sattler 2015-05-15 13:42:30 +02:00
parent b4a8bb0653
commit 2eea25873d
2 changed files with 5 additions and 3 deletions

View File

@ -121,14 +121,14 @@ void SPIClass::setBitOrder(uint8_t bitOrder) {
* @return * @return
*/ */
static uint32_t ClkRegToFreq(spiClk_t * reg) { static uint32_t ClkRegToFreq(spiClk_t * reg) {
return (F_CPU / ((reg->regPre + 1) * (reg->regN + 1))); return (SPI_MAX_SPEED / ((reg->regPre + 1) * (reg->regN + 1)));
} }
void SPIClass::setFrequency(uint32_t freq) { void SPIClass::setFrequency(uint32_t freq) {
static uint32_t lastSetFrequency = 0; static uint32_t lastSetFrequency = 0;
static uint32_t lastSetRegister = 0; static uint32_t lastSetRegister = 0;
if(freq >= F_CPU) { if(freq >= SPI_MAX_SPEED) {
setClockDivider(0x80000000); setClockDivider(0x80000000);
return; return;
} }
@ -164,7 +164,7 @@ void SPIClass::setFrequency(uint32_t freq) {
reg.regN = calN; reg.regN = calN;
while(calPreVari++ <= 1) { // test different variants for Pre (we calculate in int so we miss the decimals, testing is the easyest and fastest way) while(calPreVari++ <= 1) { // test different variants for Pre (we calculate in int so we miss the decimals, testing is the easyest and fastest way)
calPre = (((F_CPU / (reg.regN + 1)) / freq) - 1) + calPreVari; calPre = (((SPI_MAX_SPEED / (reg.regN + 1)) / freq) - 1) + calPreVari;
if(calPre > 0x1FFF) { if(calPre > 0x1FFF) {
reg.regPre = 0x1FFF; // 8191 reg.regPre = 0x1FFF; // 8191
} else if(calPre <= 0) { } else if(calPre <= 0) {

View File

@ -45,6 +45,8 @@
#define SPI_CLOCK_DIV64 0x04fc1001 //250 KHz #define SPI_CLOCK_DIV64 0x04fc1001 //250 KHz
#endif #endif
#define SPI_MAX_SPEED (80000000L)
const uint8_t SPI_MODE0 = 0x00; ///< CPOL: 0 CPHA: 0 const uint8_t SPI_MODE0 = 0x00; ///< CPOL: 0 CPHA: 0
const uint8_t SPI_MODE1 = 0x01; ///< CPOL: 0 CPHA: 1 const uint8_t SPI_MODE1 = 0x01; ///< CPOL: 0 CPHA: 1
const uint8_t SPI_MODE2 = 0x10; ///< CPOL: 1 CPHA: 0 const uint8_t SPI_MODE2 = 0x10; ///< CPOL: 1 CPHA: 0