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correct sync use

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rsil doesn't require a sync,
isync  needed for processor state register
esync needed to get special register
This commit is contained in:
Makuna 2015-06-11 13:37:13 -07:00 committed by Ivan Grokhotkov
parent 87abcf380e
commit 28a5a4c97e
2 changed files with 4 additions and 4 deletions
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6
cores/esp8266/Arduino.h
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@ -143,13 +143,13 @@ void ets_intr_unlock();
// level 15 will disable ALL interrupts,
// level 0 will disable most software interrupts
//
#define xt_disable_interrupts(state, level) __asm__ __volatile__("rsil %0," __STRINGIFY(level) "; esync; isync; dsync" : "=a" (state))
#define xt_enable_interrupts(state) __asm__ __volatile__("wsr %0,ps; esync" :: "a" (state) : "memory")
#define xt_disable_interrupts(state, level) __asm__ __volatile__("rsil %0," __STRINGIFY(level) : "=a" (state))
#define xt_enable_interrupts(state) __asm__ __volatile__("wsr %0,ps; isync" :: "a" (state) : "memory")
extern uint32_t interruptsState;
#define interrupts() xt_enable_interrupts(interruptsState)
#define noInterrupts() __asm__ __volatile__("rsil %0,15; esync; isync; dsync" : "=a" (interruptsState))
#define noInterrupts() __asm__ __volatile__("rsil %0,15" : "=a" (interruptsState))
#define clockCyclesPerMicrosecond() ( F_CPU / 1000000L )
#define clockCyclesToMicroseconds(a) ( (a) / clockCyclesPerMicrosecond() )

2
cores/esp8266/Esp.h
View File

@ -129,7 +129,7 @@ class EspClass {
uint32_t EspClass::getCycleCount()
{
uint32_t ccount;
__asm__ __volatile__("rsr %0,ccount":"=a" (ccount));
__asm__ __volatile__("esync; rsr %0,ccount":"=a" (ccount));
return ccount;
}