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[sam] enabling High Speed support for USB Device stack

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This commit is contained in:
Thibault RICHARD
2012-06-18 18:59:09 +02:00
parent c4198b3a6c
commit 21ee4f0774
17 changed files with 98 additions and 115 deletions
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33
hardware/arduino/sam/system/libsam/source/uotghs_device.c
View File

@@ -32,8 +32,8 @@
#if SAM3XA_SERIES
//#define TRACE_UOTGHS(x) x
#define TRACE_UOTGHS(x)
#define TRACE_UOTGHS_DEVICE(x) x
//#define TRACE_UOTGHS_DEVICE(x)
extern void (*gpf_isr)(void);
@@ -83,8 +83,9 @@ uint32_t UDD_Init(void)
//while (!Is_otg_clock_usable())
// ;
// Enable High Speed
udd_low_speed_disable();
udd_high_speed_disable();
udd_high_speed_enable();
//otg_ack_vbus_transition();
// Force Vbus interrupt in case of Vbus always with a high level
@@ -102,7 +103,7 @@ void UDD_Attach(void)
{
irqflags_t flags = cpu_irq_save();
TRACE_UOTGHS(printf("=> UDD_Attach\r\n");)
TRACE_UOTGHS_DEVICE(printf("=> UDD_Attach\r\n");)
otg_unfreeze_clock();
@@ -121,7 +122,7 @@ void UDD_Attach(void)
void UDD_Detach(void)
{
TRACE_UOTGHS(printf("=> UDD_Detach\r\n");)
TRACE_UOTGHS_DEVICE(printf("=> UDD_Detach\r\n");)
UOTGHS->UOTGHS_DEVCTRL |= UOTGHS_DEVCTRL_DETACH;
}
@@ -129,7 +130,7 @@ void UDD_InitEP( uint32_t ul_ep_nb, uint32_t ul_ep_cfg )
{
ul_ep_nb = ul_ep_nb & 0xF; // EP range is 0..9, hence mask is 0xF.
TRACE_UOTGHS(printf("=> UDD_InitEP : init EP %d\r\n", ul_ep_nb);)
TRACE_UOTGHS_DEVICE(printf("=> UDD_InitEP : init EP %lu\r\n", ul_ep_nb);)
// Configure EP
UOTGHS->UOTGHS_DEVEPTCFG[ul_ep_nb] = ul_ep_cfg;
@@ -137,7 +138,7 @@ void UDD_InitEP( uint32_t ul_ep_nb, uint32_t ul_ep_cfg )
udd_enable_endpoint(ul_ep_nb);
if (!Is_udd_endpoint_configured(ul_ep_nb)) {
TRACE_UOTGHS(printf("=> UDD_InitEP : ERROR FAILED TO INIT EP %d\r\n", ul_ep_nb);)
TRACE_UOTGHS_DEVICE(printf("=> UDD_InitEP : ERROR FAILED TO INIT EP %lu\r\n", ul_ep_nb);)
}
}
@@ -154,7 +155,7 @@ void UDD_InitEndpoints(const uint32_t* eps_table, const uint32_t ul_eps_table_si
udd_enable_endpoint(ul_ep_nb);
if (!Is_udd_endpoint_configured(ul_ep_nb)) {
TRACE_UOTGHS(printf("=> UDD_InitEP : ERROR FAILED TO INIT EP %d\r\n", ul_ep_nb);)
TRACE_UOTGHS_DEVICE(printf("=> UDD_InitEP : ERROR FAILED TO INIT EP %lu\r\n", ul_ep_nb);)
}
}
}
@@ -175,7 +176,7 @@ void UDD_WaitOUT(void)
// Send packet.
void UDD_ClearIN(void)
{
TRACE_UOTGHS(printf("=> UDD_ClearIN: sent %d bytes\r\n", ul_send_fifo_ptr[EP0]);)
TRACE_UOTGHS_DEVICE(printf("=> UDD_ClearIN: sent %lu bytes\r\n", ul_send_fifo_ptr[EP0]);)
UOTGHS->UOTGHS_DEVEPTICR[EP0] = UOTGHS_DEVEPTICR_TXINIC;
ul_send_fifo_ptr[EP0] = 0;
@@ -212,7 +213,7 @@ uint32_t UDD_Send(uint32_t ep, const void* data, uint32_t len)
uint8_t *ptr_dest = (uint8_t *) &udd_get_endpoint_fifo_access8(ep);
uint32_t i;
TRACE_UOTGHS(printf("=> UDD_Send (1): ep=%d ul_send_fifo_ptr=%d len=%d\r\n", ep, ul_send_fifo_ptr[ep], len);)
TRACE_UOTGHS_DEVICE(printf("=> UDD_Send (1): ep=%lu ul_send_fifo_ptr=%lu len=%lu\r\n", ep, ul_send_fifo_ptr[ep], len);)
if (ep == EP0)
{
@@ -233,7 +234,7 @@ uint32_t UDD_Send(uint32_t ep, const void* data, uint32_t len)
if (ep == EP0)
{
TRACE_UOTGHS(printf("=> UDD_Send (2): ep=%d ptr_dest=%d maxlen=%d\r\n", ep, ul_send_fifo_ptr[ep], EP0_SIZE);)
TRACE_UOTGHS_DEVICE(printf("=> UDD_Send (2): ep=%lu ptr_dest=%lu maxlen=%d\r\n", ep, ul_send_fifo_ptr[ep], EP0_SIZE);)
if (ul_send_fifo_ptr[ep] == EP0_SIZE)
{
UDD_ClearIN(); // Fifo is full, release this packet
@@ -256,7 +257,7 @@ void UDD_Send8(uint32_t ep, uint8_t data )
{
uint8_t *ptr_dest = (uint8_t *) &udd_get_endpoint_fifo_access8(ep);
TRACE_UOTGHS(printf("=> UDD_Send8 : ul_send_fifo_ptr=%d data=0x%x\r\n", ul_send_fifo_ptr[ep], data);)
TRACE_UOTGHS_DEVICE(printf("=> UDD_Send8 : ul_send_fifo_ptr=%lu data=0x%x\r\n", ul_send_fifo_ptr[ep], data);)
ptr_dest[ul_send_fifo_ptr[ep]] = data;
ul_send_fifo_ptr[ep] += 1;
@@ -267,7 +268,7 @@ uint8_t UDD_Recv8(uint32_t ep)
uint8_t *ptr_dest = (uint8_t *) &udd_get_endpoint_fifo_access8(ep);
uint8_t data = ptr_dest[ul_recv_fifo_ptr[ep]];
TRACE_UOTGHS(printf("=> UDD_Recv8 : ul_recv_fifo_ptr=%d\r\n", ul_recv_fifo_ptr[ep]);)
TRACE_UOTGHS_DEVICE(printf("=> UDD_Recv8 : ul_recv_fifo_ptr=%lu\r\n", ul_recv_fifo_ptr[ep]);)
ul_recv_fifo_ptr[ep] += 1;
return data;
@@ -299,7 +300,7 @@ uint32_t UDD_FifoByteCount(uint32_t ep)
void UDD_ReleaseRX(uint32_t ep)
{
TRACE_UOTGHS(puts("=> UDD_ReleaseRX\r\n");)
TRACE_UOTGHS_DEVICE(puts("=> UDD_ReleaseRX\r\n");)
UOTGHS->UOTGHS_DEVEPTICR[ep] = (UOTGHS_DEVEPTICR_NAKOUTIC | UOTGHS_DEVEPTICR_RXOUTIC);
UOTGHS->UOTGHS_DEVEPTIDR[ep] = UOTGHS_DEVEPTIDR_FIFOCONC;
ul_recv_fifo_ptr[ep] = 0;
@@ -307,7 +308,7 @@ void UDD_ReleaseRX(uint32_t ep)
void UDD_ReleaseTX(uint32_t ep)
{
TRACE_UOTGHS(printf("=> UDD_ReleaseTX ep=%d\r\n", ep);)
TRACE_UOTGHS_DEVICE(printf("=> UDD_ReleaseTX ep=%lu\r\n", ep);)
UOTGHS->UOTGHS_DEVEPTICR[ep] = (UOTGHS_DEVEPTICR_NAKINIC | UOTGHS_DEVEPTICR_RXOUTIC | UOTGHS_DEVEPTICR_TXINIC);
UOTGHS->UOTGHS_DEVEPTIDR[ep] = UOTGHS_DEVEPTIDR_FIFOCONC;
ul_send_fifo_ptr[ep] = 0;
@@ -321,7 +322,7 @@ uint32_t UDD_ReadWriteAllowed(uint32_t ep)
void UDD_SetAddress(uint32_t addr)
{
TRACE_UOTGHS(printf("=> UDD_SetAddress : setting address to %d\r\n", addr);)
TRACE_UOTGHS_DEVICE(printf("=> UDD_SetAddress : setting address to %lu\r\n", addr);)
udd_configure_address(addr);
udd_enable_address();

36
hardware/arduino/sam/system/libsam/source/uotghs_host.c
View File

@@ -32,8 +32,8 @@
#if SAM3XA_SERIES
#define TRACE_UOTGHS(x) x
//#define TRACE_UOTGHS(x)
#define TRACE_UOTGHS_HOST(x) x
//#define TRACE_UOTGHS_HOST(x)
extern void (*gpf_isr)(void);
@@ -43,7 +43,7 @@ static void UHD_ISR(void)
{
// Manage dis/connection event
if (Is_uhd_disconnection() && Is_uhd_disconnection_int_enabled()) {
TRACE_UOTGHS(printf(">>> UHD_ISR : Disconnection INT\r\n");)
TRACE_UOTGHS_HOST(printf(">>> UHD_ISR : Disconnection INT\r\n");)
uhd_ack_disconnection();
uhd_disable_disconnection_int();
// Stop reset signal, in case of disconnection during reset
@@ -59,7 +59,7 @@ static void UHD_ISR(void)
return;
}
if (Is_uhd_connection() && Is_uhd_connection_int_enabled()) {
TRACE_UOTGHS(printf(">>> UHD_ISR : Connection INT\r\n");)
TRACE_UOTGHS_HOST(printf(">>> UHD_ISR : Connection INT\r\n");)
uhd_ack_connection();
uhd_disable_connection_int();
uhd_ack_disconnection();
@@ -72,7 +72,7 @@ static void UHD_ISR(void)
// Manage Vbus error
if (Is_uhd_vbus_error_interrupt())
{
TRACE_UOTGHS(printf(">>> UHD_ISR : VBUS error INT\r\n");)
TRACE_UOTGHS_HOST(printf(">>> UHD_ISR : VBUS error INT\r\n");)
uhd_ack_vbus_error_interrupt();
uhd_state = UHD_STATE_ERROR;
return;
@@ -89,23 +89,23 @@ static void UHD_ISR(void)
otg_ack_vbus_transition();
if (Is_otg_vbus_high())
{
TRACE_UOTGHS(printf(">>> UHD_ISR : VBUS transition INT : UHD_STATE_DISCONNECT\r\n");)
TRACE_UOTGHS_HOST(printf(">>> UHD_ISR : VBUS transition INT : UHD_STATE_DISCONNECT\r\n");)
uhd_state = UHD_STATE_DISCONNECTED;
}
else
{
TRACE_UOTGHS(printf(">>> UHD_ISR : VBUS transition INT : UHD_STATE_NO_VBUS\r\n");)
TRACE_UOTGHS_HOST(printf(">>> UHD_ISR : VBUS transition INT : UHD_STATE_NO_VBUS\r\n");)
otg_freeze_clock();
uhd_state = UHD_STATE_NO_VBUS;
}
TRACE_UOTGHS(printf(">>> UHD_ISR : VBUS transition INT : done.\r\n");)
TRACE_UOTGHS_HOST(printf(">>> UHD_ISR : VBUS transition INT : done.\r\n");)
return;
}
// Other errors
if (Is_uhd_errors_interrupt())
{
TRACE_UOTGHS(printf(">>> UHD_ISR : Other error INT\r\n");)
TRACE_UOTGHS_HOST(printf(">>> UHD_ISR : Other error INT\r\n");)
uhd_ack_errors_interrupt();
return;
}
@@ -228,7 +228,7 @@ uint32_t UHD_EP0_Alloc(uint32_t ul_add, uint32_t ul_ep_size)
{
if (ul_ep_size < 8)
{
TRACE_UOTGHS(printf("/!\\ UHD_EP0_Alloc : incorrect pipe size!\r\n");)
TRACE_UOTGHS_HOST(printf("/!\\ UHD_EP0_Alloc : incorrect pipe size!\r\n");)
return 1;
}
@@ -251,7 +251,7 @@ uint32_t UHD_EP0_Alloc(uint32_t ul_add, uint32_t ul_ep_size)
if (!Is_uhd_pipe_configured(0))
{
TRACE_UOTGHS(printf("/!\\ UHD_EP0_Alloc : incorrect pipe settings!\r\n");)
TRACE_UOTGHS_HOST(printf("/!\\ UHD_EP0_Alloc : incorrect pipe settings!\r\n");)
uhd_disable_pipe(0);
return 1;
}
@@ -264,11 +264,21 @@ uint32_t UHD_EP0_Alloc(uint32_t ul_add, uint32_t ul_ep_size)
/**
* \brief Allocate FIFO for the specified pipe.
*
* \param ul_add Address of remote device for pipe 0.
* \param ul_ep_size Actual size of the FIFO in bytes.
*
* \retval 0 success.
* \retval 1 error.
*/
uint32_t UHD_EP_Alloc(uint32_t ul_pipe, uint32_t ul_addr, uint32_t ul_interval, uint32_t ul_type, uint32_t ul_dir, uint32_t ul_maxsize, uint32_t ul_bank)
{
/*
* Warning: this is a first implementation, pipe allocation is very limited.
* We should probably check maxsize and if maxsize > current size, then realloc with maxsize.
* If pipe type is changed, a pipe reset and re-configuration is required.
*/
if (Is_uhd_pipe_enabled(ul_pipe))
{
// Pipe is already allocated
@@ -355,7 +365,7 @@ void UHD_EP_Write(uint32_t ul_ep, uint32_t ul_size, uint8_t* data)
if (!Is_uhd_pipe_enabled(ul_ep))
{
// Endpoint not valid
TRACE_UOTGHS(printf("/!\\ UHD_EP_Send : pipe is not enabled!\r\n");)
TRACE_UOTGHS_HOST(printf("/!\\ UHD_EP_Send : pipe is not enabled!\r\n");)
return;
}
@@ -370,7 +380,7 @@ void UHD_EP_Send(uint32_t ul_ep, uint32_t ul_token_type)
if (!Is_uhd_pipe_enabled(ul_ep))
{
// Endpoint not valid
TRACE_UOTGHS(printf("/!\\ UHD_EP_Send : pipe %lu is not enabled!\r\n", ul_ep);)
TRACE_UOTGHS_HOST(printf("/!\\ UHD_EP_Send : pipe %lu is not enabled!\r\n", ul_ep);)
return;
}