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Migrate from astyle to clang-format (#8464)

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This commit is contained in:
Maxim Prokhorov
2022-02-20 19:23:33 +03:00
committed by Max Prokhorov
parent 46190b61f1
commit 19b7a29720
241 changed files with 15925 additions and 16197 deletions
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22
libraries/lwIP_w5500/examples/TCPClient/TCPClient.ino
View File

@ -5,32 +5,30 @@
#include <SPI.h>
#include <W5500lwIP.h>
//or #include <W5100lwIP.h>
//or #include <ENC28J60lwIP.h>
// or #include <W5100lwIP.h>
// or #include <ENC28J60lwIP.h>
#include <WiFiClient.h> // WiFiClient (-> TCPClient)
#include <WiFiClient.h> // WiFiClient (-> TCPClient)
const char* host = "djxmmx.net";
const uint16_t port = 17;
using TCPClient = WiFiClient;
#define CSPIN 16 // wemos/lolin/nodemcu D0
#define CSPIN 16 // wemos/lolin/nodemcu D0
Wiznet5500lwIP eth(CSPIN);
void setup() {
Serial.begin(115200);
SPI.begin();
SPI.setClockDivider(SPI_CLOCK_DIV4); // 4 MHz?
SPI.setClockDivider(SPI_CLOCK_DIV4); // 4 MHz?
SPI.setBitOrder(MSBFIRST);
SPI.setDataMode(SPI_MODE0);
eth.setDefault(); // use ethernet for default route
eth.setDefault(); // use ethernet for default route
if (!eth.begin()) {
Serial.println("ethernet hardware not found ... sleeping");
while (1) {
delay(1000);
}
while (1) { delay(1000); }
} else {
Serial.print("connecting ethernet");
while (!eth.connected()) {
@ -60,9 +58,7 @@ void loop() {
// This will send a string to the server
Serial.println("sending data to server");
if (client.connected()) {
client.println("hello from ESP8266");
}
if (client.connected()) { client.println("hello from ESP8266"); }
// wait for data to be available
unsigned long timeout = millis();
@ -89,7 +85,7 @@ void loop() {
client.stop();
if (wait) {
delay(300000); // execute once every 5 minutes, don't flood remote service
delay(300000); // execute once every 5 minutes, don't flood remote service
}
wait = true;
}

2
libraries/lwIP_w5500/src/W5500lwIP.h
View File

@ -7,4 +7,4 @@
using Wiznet5500lwIP = LwipIntfDev<Wiznet5500>;
#endif // _W5500LWIP_H
#endif // _W5500LWIP_H

35
libraries/lwIP_w5500/src/utility/w5500.cpp
View File

@ -35,7 +35,6 @@
#include <SPI.h>
#include "w5500.h"
uint8_t Wiznet5500::wizchip_read(uint8_t block, uint16_t address)
{
uint8_t ret;
@ -95,10 +94,11 @@ void Wiznet5500::wizchip_write(uint8_t block, uint16_t address, uint8_t wb)
void Wiznet5500::wizchip_write_word(uint8_t block, uint16_t address, uint16_t word)
{
wizchip_write(block, address, (uint8_t)(word >> 8));
wizchip_write(block, address + 1, (uint8_t) word);
wizchip_write(block, address + 1, (uint8_t)word);
}
void Wiznet5500::wizchip_write_buf(uint8_t block, uint16_t address, const uint8_t* pBuf, uint16_t len)
void Wiznet5500::wizchip_write_buf(uint8_t block, uint16_t address, const uint8_t* pBuf,
uint16_t len)
{
uint16_t i;
@ -123,7 +123,8 @@ void Wiznet5500::setSn_CR(uint8_t cr)
wizchip_write(BlockSelectSReg, Sn_CR, cr);
// Now wait for the command to complete
while (wizchip_read(BlockSelectSReg, Sn_CR));
while (wizchip_read(BlockSelectSReg, Sn_CR))
;
}
uint16_t Wiznet5500::getSn_TX_FSR()
@ -140,7 +141,6 @@ uint16_t Wiznet5500::getSn_TX_FSR()
return val;
}
uint16_t Wiznet5500::getSn_RX_RSR()
{
uint16_t val = 0, val1 = 0;
@ -155,7 +155,7 @@ uint16_t Wiznet5500::getSn_RX_RSR()
return val;
}
void Wiznet5500::wizchip_send_data(const uint8_t *wizdata, uint16_t len)
void Wiznet5500::wizchip_send_data(const uint8_t* wizdata, uint16_t len)
{
uint16_t ptr = 0;
@ -171,7 +171,7 @@ void Wiznet5500::wizchip_send_data(const uint8_t *wizdata, uint16_t len)
setSn_TX_WR(ptr);
}
void Wiznet5500::wizchip_recv_data(uint8_t *wizdata, uint16_t len)
void Wiznet5500::wizchip_recv_data(uint8_t* wizdata, uint16_t len)
{
uint16_t ptr;
@ -198,7 +198,7 @@ void Wiznet5500::wizchip_recv_ignore(uint16_t len)
void Wiznet5500::wizchip_sw_reset()
{
setMR(MR_RST);
getMR(); // for delay
getMR(); // for delay
setSHAR(_mac_address);
}
@ -244,7 +244,7 @@ void Wiznet5500::wizphy_reset()
int8_t Wiznet5500::wizphy_setphypmode(uint8_t pmode)
{
uint8_t tmp = 0;
tmp = getPHYCFGR();
tmp = getPHYCFGR();
if ((tmp & PHYCFGR_OPMD) == 0)
{
return -1;
@ -278,14 +278,12 @@ int8_t Wiznet5500::wizphy_setphypmode(uint8_t pmode)
return -1;
}
Wiznet5500::Wiznet5500(int8_t cs, SPIClass& spi, int8_t intr):
_spi(spi), _cs(cs)
Wiznet5500::Wiznet5500(int8_t cs, SPIClass& spi, int8_t intr) : _spi(spi), _cs(cs)
{
(void)intr;
}
boolean Wiznet5500::begin(const uint8_t *mac_address)
boolean Wiznet5500::begin(const uint8_t* mac_address)
{
memcpy(_mac_address, mac_address, 6);
@ -329,10 +327,11 @@ void Wiznet5500::end()
setSn_IR(0xFF);
// Wait for socket to change to closed
while (getSn_SR() != SOCK_CLOSED);
while (getSn_SR() != SOCK_CLOSED)
;
}
uint16_t Wiznet5500::readFrame(uint8_t *buffer, uint16_t bufsize)
uint16_t Wiznet5500::readFrame(uint8_t* buffer, uint16_t bufsize)
{
uint16_t data_len = readFrameSize();
@ -360,7 +359,7 @@ uint16_t Wiznet5500::readFrameSize()
return 0;
}
uint8_t head[2];
uint8_t head[2];
uint16_t data_len = 0;
wizchip_recv_data(head, 2);
@ -379,7 +378,7 @@ void Wiznet5500::discardFrame(uint16_t framesize)
setSn_CR(Sn_CR_RECV);
}
uint16_t Wiznet5500::readFrameData(uint8_t *buffer, uint16_t framesize)
uint16_t Wiznet5500::readFrameData(uint8_t* buffer, uint16_t framesize)
{
wizchip_recv_data(buffer, framesize);
setSn_CR(Sn_CR_RECV);
@ -402,7 +401,7 @@ uint16_t Wiznet5500::readFrameData(uint8_t *buffer, uint16_t framesize)
#endif
}
uint16_t Wiznet5500::sendFrame(const uint8_t *buf, uint16_t len)
uint16_t Wiznet5500::sendFrame(const uint8_t* buf, uint16_t len)
{
// Wait for space in the transmit buffer
while (1)

265
libraries/lwIP_w5500/src/utility/w5500.h
View File

@ -39,11 +39,8 @@
#include <Arduino.h>
#include <SPI.h>
class Wiznet5500
{
public:
/**
Constructor that uses the default hardware SPI pins
@ -51,7 +48,6 @@ public:
*/
Wiznet5500(int8_t cs = SS, SPIClass& spi = SPI, int8_t intr = -1);
/**
Initialise the Ethernet controller
Must be called before sending or receiving Ethernet frames
@ -59,7 +55,7 @@ public:
@param address the local MAC address for the Ethernet interface
@return Returns true if setting up the Ethernet interface was successful
*/
boolean begin(const uint8_t *address);
boolean begin(const uint8_t* address);
/**
Shut down the Ethernet controlled
@ -72,7 +68,7 @@ public:
@param datalen the length of the data in the packet
@return the number of bytes transmitted
*/
uint16_t sendFrame(const uint8_t *data, uint16_t datalen);
uint16_t sendFrame(const uint8_t* data, uint16_t datalen);
/**
Read an Ethernet frame
@ -81,10 +77,9 @@ public:
@return the length of the received packet
or 0 if no packet was received
*/
uint16_t readFrame(uint8_t *buffer, uint16_t bufsize);
uint16_t readFrame(uint8_t* buffer, uint16_t bufsize);
protected:
static constexpr bool interruptIsPossible()
{
return false;
@ -112,11 +107,9 @@ protected:
@return the length of the received frame
or 0 if a problem occurred
*/
uint16_t readFrameData(uint8_t *frame, uint16_t framesize);
uint16_t readFrameData(uint8_t* frame, uint16_t framesize);
private:
//< SPI interface Read operation in Control Phase
static const uint8_t AccessModeRead = (0x00 << 2);
@ -135,16 +128,14 @@ private:
//< Socket 0 Rx buffer address block
static const uint8_t BlockSelectRxBuf = (0x03 << 3);
SPIClass& _spi;
int8_t _cs;
uint8_t _mac_address[6];
int8_t _cs;
uint8_t _mac_address[6];
/**
Default function to select chip.
@note This function help not to access wrong address. If you do not describe this function or register any functions,
null function is called.
@note This function help not to access wrong address. If you do not describe this function
or register any functions, null function is called.
*/
inline void wizchip_cs_select()
{
@ -153,8 +144,8 @@ private:
/**
Default function to deselect chip.
@note This function help not to access wrong address. If you do not describe this function or register any functions,
null function is called.
@note This function help not to access wrong address. If you do not describe this function
or register any functions, null function is called.
*/
inline void wizchip_cs_deselect()
{
@ -163,8 +154,8 @@ private:
/**
Default function to read in SPI interface.
@note This function help not to access wrong address. If you do not describe this function or register any functions,
null function is called.
@note This function help not to access wrong address. If you do not describe this function
or register any functions, null function is called.
*/
inline uint8_t wizchip_spi_read_byte()
{
@ -173,15 +164,14 @@ private:
/**
Default function to write in SPI interface.
@note This function help not to access wrong address. If you do not describe this function or register any functions,
null function is called.
@note This function help not to access wrong address. If you do not describe this function
or register any functions, null function is called.
*/
inline void wizchip_spi_write_byte(uint8_t wb)
{
_spi.transfer(wb);
}
/**
Read a 1 byte value from a register.
@param address Register address
@ -240,7 +230,6 @@ private:
*/
uint16_t getSn_RX_RSR();
/**
Reset WIZCHIP by softly.
*/
@ -262,7 +251,8 @@ private:
void wizphy_reset();
/**
set the power mode of phy inside WIZCHIP. Refer to @ref PHYCFGR in W5500, @ref PHYSTATUS in W5200
set the power mode of phy inside WIZCHIP. Refer to @ref PHYCFGR in W5500, @ref PHYSTATUS in
W5200
@param pmode Settig value of power down mode.
*/
int8_t wizphy_setphypmode(uint8_t pmode);
@ -271,15 +261,15 @@ private:
It copies data to internal TX memory
@details This function reads the Tx write pointer register and after that,
it copies the <i>wizdata(pointer buffer)</i> of the length of <i>len(variable)</i> bytes to internal TX memory
and updates the Tx write pointer register.
This function is being called by send() and sendto() function also.
it copies the <i>wizdata(pointer buffer)</i> of the length of <i>len(variable)</i> bytes to
internal TX memory and updates the Tx write pointer register. This function is being called
by send() and sendto() function also.
@param wizdata Pointer buffer to write data
@param len Data length
@sa wizchip_recv_data()
*/
void wizchip_send_data(const uint8_t *wizdata, uint16_t len);
void wizchip_send_data(const uint8_t* wizdata, uint16_t len);
/**
It copies data to your buffer from internal RX memory
@ -293,183 +283,180 @@ private:
@param len Data length
@sa wizchip_send_data()
*/
void wizchip_recv_data(uint8_t *wizdata, uint16_t len);
void wizchip_recv_data(uint8_t* wizdata, uint16_t len);
/**
It discard the received data in RX memory.
@details It discards the data of the length of <i>len(variable)</i> bytes in internal RX memory.
@details It discards the data of the length of <i>len(variable)</i> bytes in internal RX
memory.
@param len Data length
*/
void wizchip_recv_ignore(uint16_t len);
/** Common registers */
enum
{
MR = 0x0000, ///< Mode Register address (R/W)
SHAR = 0x0009, ///< Source MAC Register address (R/W)
MR = 0x0000, ///< Mode Register address (R/W)
SHAR = 0x0009, ///< Source MAC Register address (R/W)
INTLEVEL = 0x0013, ///< Set Interrupt low level timer register address (R/W)
IR = 0x0015, ///< Interrupt Register (R/W)
_IMR_ = 0x0016, ///< Interrupt mask register (R/W)
SIR = 0x0017, ///< Socket Interrupt Register (R/W)
SIMR = 0x0018, ///< Socket Interrupt Mask Register (R/W)
_RTR_ = 0x0019, ///< Timeout register address (1 is 100us) (R/W)
_RCR_ = 0x001B, ///< Retry count register (R/W)
UIPR = 0x0028, ///< Unreachable IP register address in UDP mode (R)
UPORTR = 0x002C, ///< Unreachable Port register address in UDP mode (R)
PHYCFGR = 0x002E, ///< PHY Status Register (R/W)
IR = 0x0015, ///< Interrupt Register (R/W)
_IMR_ = 0x0016, ///< Interrupt mask register (R/W)
SIR = 0x0017, ///< Socket Interrupt Register (R/W)
SIMR = 0x0018, ///< Socket Interrupt Mask Register (R/W)
_RTR_ = 0x0019, ///< Timeout register address (1 is 100us) (R/W)
_RCR_ = 0x001B, ///< Retry count register (R/W)
UIPR = 0x0028, ///< Unreachable IP register address in UDP mode (R)
UPORTR = 0x002C, ///< Unreachable Port register address in UDP mode (R)
PHYCFGR = 0x002E, ///< PHY Status Register (R/W)
VERSIONR = 0x0039, ///< Chip version register address (R)
};
/** Socket registers */
enum
{
Sn_MR = 0x0000, ///< Socket Mode register (R/W)
Sn_CR = 0x0001, ///< Socket command register (R/W)
Sn_IR = 0x0002, ///< Socket interrupt register (R)
Sn_SR = 0x0003, ///< Socket status register (R)
Sn_PORT = 0x0004, ///< Source port register (R/W)
Sn_DHAR = 0x0006, ///< Peer MAC register address (R/W)
Sn_DIPR = 0x000C, ///< Peer IP register address (R/W)
Sn_DPORT = 0x0010, ///< Peer port register address (R/W)
Sn_MSSR = 0x0012, ///< Maximum Segment Size(Sn_MSSR0) register address (R/W)
Sn_TOS = 0x0015, ///< IP Type of Service(TOS) Register (R/W)
Sn_TTL = 0x0016, ///< IP Time to live(TTL) Register (R/W)
Sn_MR = 0x0000, ///< Socket Mode register (R/W)
Sn_CR = 0x0001, ///< Socket command register (R/W)
Sn_IR = 0x0002, ///< Socket interrupt register (R)
Sn_SR = 0x0003, ///< Socket status register (R)
Sn_PORT = 0x0004, ///< Source port register (R/W)
Sn_DHAR = 0x0006, ///< Peer MAC register address (R/W)
Sn_DIPR = 0x000C, ///< Peer IP register address (R/W)
Sn_DPORT = 0x0010, ///< Peer port register address (R/W)
Sn_MSSR = 0x0012, ///< Maximum Segment Size(Sn_MSSR0) register address (R/W)
Sn_TOS = 0x0015, ///< IP Type of Service(TOS) Register (R/W)
Sn_TTL = 0x0016, ///< IP Time to live(TTL) Register (R/W)
Sn_RXBUF_SIZE = 0x001E, ///< Receive memory size register (R/W)
Sn_TXBUF_SIZE = 0x001F, ///< Transmit memory size register (R/W)
Sn_TX_FSR = 0x0020, ///< Transmit free memory size register (R)
Sn_TX_RD = 0x0022, ///< Transmit memory read pointer register address (R)
Sn_TX_WR = 0x0024, ///< Transmit memory write pointer register address (R/W)
Sn_RX_RSR = 0x0026, ///< Received data size register (R)
Sn_RX_RD = 0x0028, ///< Read point of Receive memory (R/W)
Sn_RX_WR = 0x002A, ///< Write point of Receive memory (R)
Sn_IMR = 0x002C, ///< Socket interrupt mask register (R)
Sn_FRAG = 0x002D, ///< Fragment field value in IP header register (R/W)
Sn_KPALVTR = 0x002F, ///< Keep Alive Timer register (R/W)
Sn_TX_FSR = 0x0020, ///< Transmit free memory size register (R)
Sn_TX_RD = 0x0022, ///< Transmit memory read pointer register address (R)
Sn_TX_WR = 0x0024, ///< Transmit memory write pointer register address (R/W)
Sn_RX_RSR = 0x0026, ///< Received data size register (R)
Sn_RX_RD = 0x0028, ///< Read point of Receive memory (R/W)
Sn_RX_WR = 0x002A, ///< Write point of Receive memory (R)
Sn_IMR = 0x002C, ///< Socket interrupt mask register (R)
Sn_FRAG = 0x002D, ///< Fragment field value in IP header register (R/W)
Sn_KPALVTR = 0x002F, ///< Keep Alive Timer register (R/W)
};
/** Mode register values */
enum
{
MR_RST = 0x80, ///< Reset
MR_WOL = 0x20, ///< Wake on LAN
MR_PB = 0x10, ///< Ping block
MR_RST = 0x80, ///< Reset
MR_WOL = 0x20, ///< Wake on LAN
MR_PB = 0x10, ///< Ping block
MR_PPPOE = 0x08, ///< Enable PPPoE
MR_FARP = 0x02, ///< Enable UDP_FORCE_ARP CHECK
MR_FARP = 0x02, ///< Enable UDP_FORCE_ARP CHECK
};
/* Interrupt Register values */
enum
{
IR_CONFLICT = 0x80, ///< Check IP conflict
IR_UNREACH = 0x40, ///< Get the destination unreachable message in UDP sending
IR_PPPoE = 0x20, ///< Get the PPPoE close message
IR_MP = 0x10, ///< Get the magic packet interrupt
IR_UNREACH = 0x40, ///< Get the destination unreachable message in UDP sending
IR_PPPoE = 0x20, ///< Get the PPPoE close message
IR_MP = 0x10, ///< Get the magic packet interrupt
};
/* Interrupt Mask Register values */
enum
{
IM_IR7 = 0x80, ///< IP Conflict Interrupt Mask
IM_IR6 = 0x40, ///< Destination unreachable Interrupt Mask
IM_IR5 = 0x20, ///< PPPoE Close Interrupt Mask
IM_IR4 = 0x10, ///< Magic Packet Interrupt Mask
IM_IR7 = 0x80, ///< IP Conflict Interrupt Mask
IM_IR6 = 0x40, ///< Destination unreachable Interrupt Mask
IM_IR5 = 0x20, ///< PPPoE Close Interrupt Mask
IM_IR4 = 0x10, ///< Magic Packet Interrupt Mask
};
/** Socket Mode Register values @ref Sn_MR */
enum
{
Sn_MR_CLOSE = 0x00, ///< Unused socket
Sn_MR_TCP = 0x01, ///< TCP
Sn_MR_UDP = 0x02, ///< UDP
Sn_MR_MACRAW = 0x04, ///< MAC LAYER RAW SOCK
Sn_MR_UCASTB = 0x10, ///< Unicast Block in UDP Multicasting
Sn_MR_ND = 0x20, ///< No Delayed Ack(TCP), Multicast flag
Sn_MR_BCASTB = 0x40, ///< Broadcast block in UDP Multicasting
Sn_MR_MULTI = 0x80, ///< Support UDP Multicasting
Sn_MR_MIP6B = 0x10, ///< IPv6 packet Blocking in @ref Sn_MR_MACRAW mode
Sn_MR_MMB = 0x20, ///< Multicast Blocking in @ref Sn_MR_MACRAW mode
Sn_MR_MFEN = 0x80, ///< MAC filter enable in @ref Sn_MR_MACRAW mode
Sn_MR_CLOSE = 0x00, ///< Unused socket
Sn_MR_TCP = 0x01, ///< TCP
Sn_MR_UDP = 0x02, ///< UDP
Sn_MR_MACRAW = 0x04, ///< MAC LAYER RAW SOCK
Sn_MR_UCASTB = 0x10, ///< Unicast Block in UDP Multicasting
Sn_MR_ND = 0x20, ///< No Delayed Ack(TCP), Multicast flag
Sn_MR_BCASTB = 0x40, ///< Broadcast block in UDP Multicasting
Sn_MR_MULTI = 0x80, ///< Support UDP Multicasting
Sn_MR_MIP6B = 0x10, ///< IPv6 packet Blocking in @ref Sn_MR_MACRAW mode
Sn_MR_MMB = 0x20, ///< Multicast Blocking in @ref Sn_MR_MACRAW mode
Sn_MR_MFEN = 0x80, ///< MAC filter enable in @ref Sn_MR_MACRAW mode
};
/** Socket Command Register values */
enum
{
Sn_CR_OPEN = 0x01, ///< Initialise or open socket
Sn_CR_LISTEN = 0x02, ///< Wait connection request in TCP mode (Server mode)
Sn_CR_CONNECT = 0x04, ///< Send connection request in TCP mode (Client mode)
Sn_CR_DISCON = 0x08, ///< Send closing request in TCP mode
Sn_CR_CLOSE = 0x10, ///< Close socket
Sn_CR_SEND = 0x20, ///< Update TX buffer pointer and send data
Sn_CR_SEND_MAC = 0x21, ///< Send data with MAC address, so without ARP process
Sn_CR_SEND_KEEP = 0x22, ///< Send keep alive message
Sn_CR_RECV = 0x40, ///< Update RX buffer pointer and receive data
Sn_CR_OPEN = 0x01, ///< Initialise or open socket
Sn_CR_LISTEN = 0x02, ///< Wait connection request in TCP mode (Server mode)
Sn_CR_CONNECT = 0x04, ///< Send connection request in TCP mode (Client mode)
Sn_CR_DISCON = 0x08, ///< Send closing request in TCP mode
Sn_CR_CLOSE = 0x10, ///< Close socket
Sn_CR_SEND = 0x20, ///< Update TX buffer pointer and send data
Sn_CR_SEND_MAC = 0x21, ///< Send data with MAC address, so without ARP process
Sn_CR_SEND_KEEP = 0x22, ///< Send keep alive message
Sn_CR_RECV = 0x40, ///< Update RX buffer pointer and receive data
};
/** Socket Interrupt register values */
enum
{
Sn_IR_CON = 0x01, ///< CON Interrupt
Sn_IR_DISCON = 0x02, ///< DISCON Interrupt
Sn_IR_RECV = 0x04, ///< RECV Interrupt
Sn_IR_CON = 0x01, ///< CON Interrupt
Sn_IR_DISCON = 0x02, ///< DISCON Interrupt
Sn_IR_RECV = 0x04, ///< RECV Interrupt
Sn_IR_TIMEOUT = 0x08, ///< TIMEOUT Interrupt
Sn_IR_SENDOK = 0x10, ///< SEND_OK Interrupt
Sn_IR_SENDOK = 0x10, ///< SEND_OK Interrupt
};
/** Socket Status Register values */
enum
{
SOCK_CLOSED = 0x00, ///< Closed
SOCK_INIT = 0x13, ///< Initiate state
SOCK_LISTEN = 0x14, ///< Listen state
SOCK_SYNSENT = 0x15, ///< Connection state
SOCK_SYNRECV = 0x16, ///< Connection state
SOCK_ESTABLISHED = 0x17, ///< Success to connect
SOCK_FIN_WAIT = 0x18, ///< Closing state
SOCK_CLOSING = 0x1A, ///< Closing state
SOCK_TIME_WAIT = 0x1B, ///< Closing state
SOCK_CLOSE_WAIT = 0x1C, ///< Closing state
SOCK_LAST_ACK = 0x1D, ///< Closing state
SOCK_UDP = 0x22, ///< UDP socket
SOCK_MACRAW = 0x42, ///< MAC raw mode socket
SOCK_CLOSED = 0x00, ///< Closed
SOCK_INIT = 0x13, ///< Initiate state
SOCK_LISTEN = 0x14, ///< Listen state
SOCK_SYNSENT = 0x15, ///< Connection state
SOCK_SYNRECV = 0x16, ///< Connection state
SOCK_ESTABLISHED = 0x17, ///< Success to connect
SOCK_FIN_WAIT = 0x18, ///< Closing state
SOCK_CLOSING = 0x1A, ///< Closing state
SOCK_TIME_WAIT = 0x1B, ///< Closing state
SOCK_CLOSE_WAIT = 0x1C, ///< Closing state
SOCK_LAST_ACK = 0x1D, ///< Closing state
SOCK_UDP = 0x22, ///< UDP socket
SOCK_MACRAW = 0x42, ///< MAC raw mode socket
};
/* PHYCFGR register value */
enum
{
PHYCFGR_RST = ~(1 << 7), //< For PHY reset, must operate AND mask.
PHYCFGR_OPMD = (1 << 6), // Configre PHY with OPMDC value
PHYCFGR_OPMDC_ALLA = (7 << 3),
PHYCFGR_RST = ~(1 << 7), //< For PHY reset, must operate AND mask.
PHYCFGR_OPMD = (1 << 6), // Configre PHY with OPMDC value
PHYCFGR_OPMDC_ALLA = (7 << 3),
PHYCFGR_OPMDC_PDOWN = (6 << 3),
PHYCFGR_OPMDC_NA = (5 << 3),
PHYCFGR_OPMDC_NA = (5 << 3),
PHYCFGR_OPMDC_100FA = (4 << 3),
PHYCFGR_OPMDC_100F = (3 << 3),
PHYCFGR_OPMDC_100H = (2 << 3),
PHYCFGR_OPMDC_10F = (1 << 3),
PHYCFGR_OPMDC_10H = (0 << 3),
PHYCFGR_DPX_FULL = (1 << 2),
PHYCFGR_DPX_HALF = (0 << 2),
PHYCFGR_SPD_100 = (1 << 1),
PHYCFGR_SPD_10 = (0 << 1),
PHYCFGR_LNK_ON = (1 << 0),
PHYCFGR_LNK_OFF = (0 << 0),
PHYCFGR_OPMDC_100F = (3 << 3),
PHYCFGR_OPMDC_100H = (2 << 3),
PHYCFGR_OPMDC_10F = (1 << 3),
PHYCFGR_OPMDC_10H = (0 << 3),
PHYCFGR_DPX_FULL = (1 << 2),
PHYCFGR_DPX_HALF = (0 << 2),
PHYCFGR_SPD_100 = (1 << 1),
PHYCFGR_SPD_10 = (0 << 1),
PHYCFGR_LNK_ON = (1 << 0),
PHYCFGR_LNK_OFF = (0 << 0),
};
enum
{
PHY_SPEED_10 = 0, ///< Link Speed 10
PHY_SPEED_100 = 1, ///< Link Speed 100
PHY_SPEED_10 = 0, ///< Link Speed 10
PHY_SPEED_100 = 1, ///< Link Speed 100
PHY_DUPLEX_HALF = 0, ///< Link Half-Duplex
PHY_DUPLEX_FULL = 1, ///< Link Full-Duplex
PHY_LINK_OFF = 0, ///< Link Off
PHY_LINK_ON = 1, ///< Link On
PHY_POWER_NORM = 0, ///< PHY power normal mode
PHY_POWER_DOWN = 1, ///< PHY power down mode
PHY_LINK_OFF = 0, ///< Link Off
PHY_LINK_ON = 1, ///< Link On
PHY_POWER_NORM = 0, ///< PHY power normal mode
PHY_POWER_DOWN = 1, ///< PHY power down mode
};
/**
Set Mode Register
@param (uint8_t)mr The value to be set.
@ -492,7 +479,8 @@ private:
/**
Set local MAC address
@param (uint8_t*)shar Pointer variable to set local MAC address. It should be allocated 6 bytes.
@param (uint8_t*)shar Pointer variable to set local MAC address. It should be allocated 6
bytes.
@sa getSHAR()
*/
inline void setSHAR(const uint8_t* macaddr)
@ -502,7 +490,8 @@ private:
/**
Get local MAC address
@param (uint8_t*)shar Pointer variable to get local MAC address. It should be allocated 6 bytes.
@param (uint8_t*)shar Pointer variable to get local MAC address. It should be allocated 6
bytes.
@sa setSHAR()
*/
inline void getSHAR(uint8_t* macaddr)
@ -764,4 +753,4 @@ private:
}
};
#endif // W5500_H
#endif // W5500_H