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Move timer ISR handlers and PWM handler into RAM (fix #819)

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This commit is contained in:
Ivan Grokhotkov 2015-10-06 13:26:21 +03:00
parent 0873ae22d3
commit 0c703b3baf
2 changed files with 9 additions and 12 deletions
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9
cores/esp8266/core_esp8266_timer.c
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@ -29,7 +29,7 @@
static volatile timercallback timer1_user_cb = NULL;
void timer1_isr_handler(void *para){
void ICACHE_RAM_ATTR timer1_isr_handler(void *para){
if ((T1C & ((1 << TCAR) | (1 << TCIT))) == 0) TEIE &= ~TEIE1;//edge int disable
T1I = 0;
if (timer1_user_cb) {
@ -61,7 +61,7 @@ void timer1_enable(uint8_t divider, uint8_t int_type, uint8_t reload){
T1I = 0;
}
void timer1_write(uint32_t ticks){
void ICACHE_RAM_ATTR timer1_write(uint32_t ticks){
T1L = ((ticks)& 0x7FFFFF);
if ((T1C & (1 << TCIT)) == 0) TEIE |= TEIE1;//edge int enable
}
@ -76,7 +76,7 @@ void timer1_disable(){
static volatile timercallback timer0_user_cb = NULL;
void timer0_isr_handler(void* para){
void ICACHE_RAM_ATTR timer0_isr_handler(void* para){
if (timer0_user_cb) {
// to make ISR compatible to Arduino AVR model where interrupts are disabled
// we disable them before we call the client ISR
@ -99,6 +99,3 @@ void timer0_detachInterrupt() {
timer0_user_cb = NULL;
ETS_CCOMPARE0_DISABLE();
}

2
cores/esp8266/core_esp8266_wiring_pwm.c
View File

@ -88,7 +88,7 @@ void prep_pwm_steps(){
ETS_FRC1_INTR_ENABLE();
}
void pwm_timer_isr(){
void ICACHE_RAM_ATTR pwm_timer_isr(){
static uint8_t current_step = 0;
static uint8_t stepcount = 0;
static uint16_t steps[17];