Beinsezii f0c81562a4 Add final_sigma_zero to UniPCMultistep (#7517) ...

* Add `final_sigma_zero` to UniPCMultistep

Effectively the same trick as DDIM's `set_alpha_to_one` and
DPM's `final_sigma_type='zero'`.
Currently False by default but maybe this should be True?

* `final_sigma_zero: bool` -> `final_sigmas_type: str`

Should 1:1 match DPM Multistep now.

* Set `final_sigmas_type='sigma_min'` in UniPC UTs

2024-03-29 22:23:45 -10:00

..

fixtures

change to 2024 in the license (#6902)

2024-02-08 08:19:31 -10:00

lora

Implements Blockwise lora (#7352)

2024-03-29 21:15:57 +05:30

models

Memory clean up on all Slow Tests (#7514)

2024-03-29 14:23:28 +05:30

others

Remove distutils (#7455)

2024-03-25 06:44:53 +05:30

pipelines

Memory clean up on all Slow Tests (#7514)

2024-03-29 14:23:28 +05:30

schedulers

Add final_sigma_zero to UniPCMultistep (#7517)

2024-03-29 22:23:45 -10:00

__init__.py

fix issues with loading, add test for pipeline

2022-06-07 15:40:36 +02:00

conftest.py

change to 2024 in the license (#6902)

2024-02-08 08:19:31 -10:00