Patrick von Platen ea1fcc28a4 [SDXL] Allow SDXL LoRA to be run with less than 16GB of VRAM (#4470) ...

* correct

* correct blocks

* finish

* finish

* finish

* Apply suggestions from code review

* fix

* up

* up

* up

* Update examples/dreambooth/README_sdxl.md

Co-authored-by: Sayak Paul <spsayakpaul@gmail.com>

* Apply suggestions from code review

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Co-authored-by: Sayak Paul <spsayakpaul@gmail.com>

2023-08-04 20:06:38 +02:00

..

fixtures

Fix config prints and save, load of pipelines (#2849)

2023-04-11 13:35:42 +02:00

models

[SDXL] Allow SDXL LoRA to be run with less than 16GB of VRAM (#4470)

2023-08-04 20:06:38 +02:00

others

[Tests] add test for pipeline import. (#4276)

2023-07-28 00:08:15 +05:30

pipelines

Cleanup Pass on flaky slow tests for Stable Diffusion (#4455)

2023-08-04 10:24:56 +02:00

schedulers

Add Recent Timestep Scheduling Improvements to DDIM Inverse Scheduler (#3865)

2023-07-18 11:35:16 +02:00

__init__.py

fix issues with loading, add test for pipeline

2022-06-07 15:40:36 +02:00

conftest.py

[Copyright] 2023 (#2524)

2023-03-01 10:31:00 +01:00